X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=arch%2Farm%2Fcpu%2Farmv8%2Ffsl-layerscape%2FKconfig;h=f48481f465a56b89b33ff60e83460d549f5e0bba;hb=da206916a14fc8ab8962763c47673128a29b4b9c;hp=cdeef26fe5d4fd27f4ab55bd81070f1ea96232ae;hpb=470135be276b2d92c6da464c68839202d4ff0d08;p=platform%2Fkernel%2Fu-boot.git diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index cdeef26..f48481f 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -1,54 +1,131 @@ config ARCH_LS1012A bool select ARMV8_SET_SMPEN + select ARM_ERRATA_855873 if !TFABOOT + select FSL_LAYERSCAPE select FSL_LSCH2 + select SYS_FSL_SRDS_1 + select SYS_HAS_SERDES select SYS_FSL_DDR_BE select SYS_FSL_MMDC select SYS_FSL_ERRATUM_A010315 + select SYS_FSL_ERRATUM_A009798 + select SYS_FSL_ERRATUM_A008997 + select SYS_FSL_ERRATUM_A009007 + select SYS_FSL_ERRATUM_A009008 select ARCH_EARLY_INIT_R select BOARD_EARLY_INIT_F + select SYS_I2C_MXC + select SYS_I2C_MXC_I2C1 + select SYS_I2C_MXC_I2C2 + imply PANIC_HANG config ARCH_LS1043A bool select ARMV8_SET_SMPEN + select ARM_ERRATA_855873 if !TFABOOT + select FSL_LAYERSCAPE select FSL_LSCH2 + select SYS_FSL_SRDS_1 + select SYS_HAS_SERDES select SYS_FSL_DDR select SYS_FSL_DDR_BE select SYS_FSL_DDR_VER_50 - select SYS_FSL_ERRATUM_A008850 - select SYS_FSL_ERRATUM_A009660 - select SYS_FSL_ERRATUM_A009663 + select SYS_FSL_ERRATUM_A008850 if !TFABOOT + select SYS_FSL_ERRATUM_A008997 + select SYS_FSL_ERRATUM_A009007 + select SYS_FSL_ERRATUM_A009008 + select SYS_FSL_ERRATUM_A009660 if !TFABOOT + select SYS_FSL_ERRATUM_A009663 if !TFABOOT + select SYS_FSL_ERRATUM_A009798 select SYS_FSL_ERRATUM_A009929 - select SYS_FSL_ERRATUM_A009942 + select SYS_FSL_ERRATUM_A009942 if !TFABOOT select SYS_FSL_ERRATUM_A010315 select SYS_FSL_ERRATUM_A010539 select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_DDR4 select ARCH_EARLY_INIT_R select BOARD_EARLY_INIT_F - imply SCSI + select SYS_I2C_MXC + select SYS_I2C_MXC_I2C1 + select SYS_I2C_MXC_I2C2 + select SYS_I2C_MXC_I2C3 + select SYS_I2C_MXC_I2C4 imply CMD_PCI config ARCH_LS1046A bool select ARMV8_SET_SMPEN + select FSL_LAYERSCAPE select FSL_LSCH2 + select SYS_FSL_SRDS_1 + select SYS_HAS_SERDES select SYS_FSL_DDR select SYS_FSL_DDR_BE select SYS_FSL_DDR_VER_50 - select SYS_FSL_ERRATUM_A008336 - select SYS_FSL_ERRATUM_A008511 - select SYS_FSL_ERRATUM_A008850 + select SYS_FSL_ERRATUM_A008336 if !TFABOOT + select SYS_FSL_ERRATUM_A008511 if !TFABOOT + select SYS_FSL_ERRATUM_A008850 if !TFABOOT + select SYS_FSL_ERRATUM_A008997 + select SYS_FSL_ERRATUM_A009007 + select SYS_FSL_ERRATUM_A009008 + select SYS_FSL_ERRATUM_A009798 select SYS_FSL_ERRATUM_A009801 - select SYS_FSL_ERRATUM_A009803 - select SYS_FSL_ERRATUM_A009942 - select SYS_FSL_ERRATUM_A010165 + select SYS_FSL_ERRATUM_A009803 if !TFABOOT + select SYS_FSL_ERRATUM_A009942 if !TFABOOT + select SYS_FSL_ERRATUM_A010165 if !TFABOOT select SYS_FSL_ERRATUM_A010539 select SYS_FSL_HAS_DDR4 select SYS_FSL_SRDS_2 select ARCH_EARLY_INIT_R select BOARD_EARLY_INIT_F + select SYS_I2C_MXC + select SYS_I2C_MXC_I2C1 + select SYS_I2C_MXC_I2C2 + select SYS_I2C_MXC_I2C3 + select SYS_I2C_MXC_I2C4 + imply SCSI + imply SCSI_AHCI + +config ARCH_LS1088A + bool + select ARMV8_SET_SMPEN + select ARM_ERRATA_855873 if !TFABOOT + select FSL_LAYERSCAPE + select FSL_LSCH3 + select SYS_FSL_SRDS_1 + select SYS_HAS_SERDES + select SYS_FSL_DDR + select SYS_FSL_DDR_LE + select SYS_FSL_DDR_VER_50 + select SYS_FSL_EC1 + select SYS_FSL_EC2 + select SYS_FSL_ERRATUM_A009803 if !TFABOOT + select SYS_FSL_ERRATUM_A009942 if !TFABOOT + select SYS_FSL_ERRATUM_A010165 if !TFABOOT + select SYS_FSL_ERRATUM_A008511 if !TFABOOT + select SYS_FSL_ERRATUM_A008850 if !TFABOOT + select SYS_FSL_ERRATUM_A009007 + select SYS_FSL_HAS_CCI400 + select SYS_FSL_HAS_DDR4 + select SYS_FSL_HAS_RGMII + select SYS_FSL_HAS_SEC + select SYS_FSL_SEC_COMPAT_5 + select SYS_FSL_SEC_LE + select SYS_FSL_SRDS_1 + select SYS_FSL_SRDS_2 + select FSL_TZASC_1 + select FSL_TZASC_400 + select FSL_TZPC_BP147 + select ARCH_EARLY_INIT_R + select BOARD_EARLY_INIT_F + select SYS_I2C_MXC + select SYS_I2C_MXC_I2C1 + select SYS_I2C_MXC_I2C2 + select SYS_I2C_MXC_I2C3 + select SYS_I2C_MXC_I2C4 imply SCSI + imply PANIC_HANG config ARCH_LS2080A bool @@ -57,10 +134,14 @@ config ARCH_LS2080A select ARM_ERRATA_828024 select ARM_ERRATA_829520 select ARM_ERRATA_833471 + select FSL_LAYERSCAPE select FSL_LSCH3 + select SYS_FSL_SRDS_1 + select SYS_HAS_SERDES select SYS_FSL_DDR select SYS_FSL_DDR_LE select SYS_FSL_DDR_VER_50 + select SYS_FSL_HAS_CCN504 select SYS_FSL_HAS_DP_DDR select SYS_FSL_HAS_SEC select SYS_FSL_HAS_DDR4 @@ -69,36 +150,85 @@ config ARCH_LS2080A select SYS_FSL_SRDS_2 select FSL_TZASC_1 select FSL_TZASC_2 - select SYS_FSL_ERRATUM_A008336 - select SYS_FSL_ERRATUM_A008511 - select SYS_FSL_ERRATUM_A008514 + select FSL_TZASC_400 + select FSL_TZPC_BP147 + select SYS_FSL_ERRATUM_A008336 if !TFABOOT + select SYS_FSL_ERRATUM_A008511 if !TFABOOT + select SYS_FSL_ERRATUM_A008514 if !TFABOOT select SYS_FSL_ERRATUM_A008585 + select SYS_FSL_ERRATUM_A008997 + select SYS_FSL_ERRATUM_A009007 + select SYS_FSL_ERRATUM_A009008 select SYS_FSL_ERRATUM_A009635 - select SYS_FSL_ERRATUM_A009663 + select SYS_FSL_ERRATUM_A009663 if !TFABOOT + select SYS_FSL_ERRATUM_A009798 select SYS_FSL_ERRATUM_A009801 - select SYS_FSL_ERRATUM_A009803 - select SYS_FSL_ERRATUM_A009942 - select SYS_FSL_ERRATUM_A010165 + select SYS_FSL_ERRATUM_A009803 if !TFABOOT + select SYS_FSL_ERRATUM_A009942 if !TFABOOT + select SYS_FSL_ERRATUM_A010165 if !TFABOOT select SYS_FSL_ERRATUM_A009203 select ARCH_EARLY_INIT_R select BOARD_EARLY_INIT_F + select SYS_I2C_MXC + select SYS_I2C_MXC_I2C1 + select SYS_I2C_MXC_I2C2 + select SYS_I2C_MXC_I2C3 + select SYS_I2C_MXC_I2C4 + imply DISTRO_DEFAULTS + imply PANIC_HANG + +config ARCH_LX2160A + bool + select ARMV8_SET_SMPEN + select FSL_LSCH3 + select NXP_LSCH3_2 + select SYS_HAS_SERDES + select SYS_FSL_SRDS_1 + select SYS_FSL_SRDS_2 + select SYS_NXP_SRDS_3 + select SYS_FSL_DDR + select SYS_FSL_DDR_LE + select SYS_FSL_DDR_VER_50 + select SYS_FSL_EC1 + select SYS_FSL_EC2 + select SYS_FSL_HAS_RGMII + select SYS_FSL_HAS_SEC + select SYS_FSL_HAS_CCN508 + select SYS_FSL_HAS_DDR4 + select SYS_FSL_SEC_COMPAT_5 + select SYS_FSL_SEC_LE + select ARCH_EARLY_INIT_R + select BOARD_EARLY_INIT_F + select SYS_I2C_MXC + select SYS_I2C_MXC_I2C1 + select SYS_I2C_MXC_I2C2 + select SYS_I2C_MXC_I2C3 + select SYS_I2C_MXC_I2C4 + select SYS_I2C_MXC_I2C5 + select SYS_I2C_MXC_I2C6 + select SYS_I2C_MXC_I2C7 + select SYS_I2C_MXC_I2C8 + imply DISTRO_DEFAULTS + imply PANIC_HANG + imply SCSI + imply SCSI_AHCI config FSL_LSCH2 bool + select SYS_FSL_HAS_CCI400 select SYS_FSL_HAS_SEC select SYS_FSL_SEC_COMPAT_5 select SYS_FSL_SEC_BE - select SYS_FSL_SRDS_1 - select SYS_HAS_SERDES config FSL_LSCH3 bool - select SYS_FSL_SRDS_1 - select SYS_HAS_SERDES + +config NXP_LSCH3_2 + bool config FSL_MC_ENET bool "Management Complex network" - depends on ARCH_LS2080A + depends on ARCH_LS2080A || ARCH_LS1088A || ARCH_LX2160A default y select RESV_RAM help @@ -107,6 +237,9 @@ config FSL_MC_ENET menu "Layerscape architecture" depends on FSL_LSCH2 || FSL_LSCH3 +config FSL_LAYERSCAPE + bool + config FSL_PCIE_COMPAT string "PCIe compatible of Kernel DT" depends on PCIE_LAYERSCAPE @@ -114,6 +247,8 @@ config FSL_PCIE_COMPAT default "fsl,ls1043a-pcie" if ARCH_LS1043A default "fsl,ls1046a-pcie" if ARCH_LS1046A default "fsl,ls2080a-pcie" if ARCH_LS2080A + default "fsl,ls1088a-pcie" if ARCH_LS1088A + default "fsl,lx2160a-pcie" if ARCH_LX2160A help This compatible is used to find pci controller node in Kernel DT to complete fixup. @@ -176,37 +311,6 @@ config SYS_LS_PPA_FW_IN_NAND endchoice -config SYS_LS_PPA_FW_ADDR - hex "Address of PPA firmware loading from" - depends on FSL_LS_PPA - default 0x20400000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT && ARCH_LS2080A - default 0x40400000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT - default 0x580400000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS2080A - default 0x60400000 if SYS_LS_PPA_FW_IN_XIP - default 0x400000 if SYS_LS_PPA_FW_IN_MMC - default 0x400000 if SYS_LS_PPA_FW_IN_NAND - - help - If the PPA firmware locate at XIP flash, such as NOR or - QSPI flash, this address is a directly memory-mapped. - If it is in a serial accessed flash, such as NAND and SD - card, it is a byte offset. - -config SYS_LS_PPA_ESBC_ADDR - hex "hdr address of PPA firmware loading from" - depends on FSL_LS_PPA && CHAIN_OF_TRUST - default 0x600c0000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1043A - default 0x40740000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1046A - default 0x40480000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1012A - default 0x580c40000 if SYS_LS_PPA_FW_IN_XIP && FSL_LSCH3 - default 0x700000 if SYS_LS_PPA_FW_IN_MMC - default 0x700000 if SYS_LS_PPA_FW_IN_NAND - help - If the PPA header firmware locate at XIP flash, such as NOR or - QSPI flash, this address is a directly memory-mapped. - If it is in a serial accessed flash, such as NAND and SD - card, it is a byte offset. - config LS_PPA_ESBC_HDR_SIZE hex "Length of PPA ESBC header" depends on FSL_LS_PPA && CHAIN_OF_TRUST && !SYS_LS_PPA_FW_IN_XIP @@ -217,6 +321,20 @@ config LS_PPA_ESBC_HDR_SIZE endmenu +config SYS_FSL_ERRATUM_A008997 + bool "Workaround for USB PHY erratum A008997" + +config SYS_FSL_ERRATUM_A009007 + bool + help + Workaround for USB PHY erratum A009007 + +config SYS_FSL_ERRATUM_A009008 + bool "Workaround for USB PHY erratum A009008" + +config SYS_FSL_ERRATUM_A009798 + bool "Workaround for USB PHY erratum A009798" + config SYS_FSL_ERRATUM_A010315 bool "Workaround for PCIe erratum A010315" @@ -228,6 +346,8 @@ config MAX_CPUS default 4 if ARCH_LS1043A default 4 if ARCH_LS1046A default 16 if ARCH_LS2080A + default 8 if ARCH_LS1088A + default 16 if ARCH_LX2160A default 1 help Set this number to the maximum number of possible CPUs in the SoC. @@ -236,6 +356,12 @@ config MAX_CPUS cores, count the reserved ports. This will allocate enough memory in spin table to properly handle all cores. +config EMC2305 + bool "Fan controller" + help + Enable the EMC2305 fan controller for configuration of fan + speed. + config SECURE_BOOT bool "Secure Boot" help @@ -248,12 +374,30 @@ config QSPI_AHB_INIT But some QSPI flash size up to 64MBytes, so initialize the QSPI AHB bus for those flashes to support the full QSPI flash size. +config SYS_CCI400_OFFSET + hex "Offset for CCI400 base" + depends on SYS_FSL_HAS_CCI400 + default 0x3090000 if ARCH_LS1088A + default 0x180000 if FSL_LSCH2 + help + Offset for CCI400 base + CCI400 base addr = CCSRBAR + CCI400_OFFSET + config SYS_FSL_IFC_BANK_COUNT int "Maximum banks of Integrated flash controller" - depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A + depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A || ARCH_LS1088A default 4 if ARCH_LS1043A default 4 if ARCH_LS1046A - default 8 if ARCH_LS2080A + default 8 if ARCH_LS2080A || ARCH_LS1088A + +config SYS_FSL_HAS_CCI400 + bool + +config SYS_FSL_HAS_CCN504 + bool + +config SYS_FSL_HAS_CCN508 + bool config SYS_FSL_HAS_DP_DDR bool @@ -264,6 +408,9 @@ config SYS_FSL_SRDS_1 config SYS_FSL_SRDS_2 bool +config SYS_NXP_SRDS_3 + bool + config SYS_HAS_SERDES bool @@ -273,6 +420,11 @@ config FSL_TZASC_1 config FSL_TZASC_2 bool +config FSL_TZASC_400 + bool + +config FSL_TZPC_BP147 + bool endmenu menu "Layerscape clock tree configuration" @@ -296,6 +448,7 @@ config SYS_FSL_PCLK_DIV int "Platform clock divider" default 1 if ARCH_LS1043A default 1 if ARCH_LS1046A + default 1 if ARCH_LS1088A default 2 help This is the divider that is used to derive Platform clock from @@ -313,6 +466,7 @@ config SYS_FSL_DSPI_CLK_DIV config SYS_FSL_DUART_CLK_DIV int "DUART clock divider" default 1 if ARCH_LS1043A + default 4 if ARCH_LX2160A default 2 help This is the divider that is used to derive DUART clock from Platform @@ -350,6 +504,14 @@ config SYS_FSL_SDHC_CLK_DIV help This is the divider that is used to derive SDHC clock from Platform clock, in another word SDHC_clk = Platform_clk / this_divider. + +config SYS_FSL_QMAN_CLK_DIV + int "QMAN clock divider" + default 1 if ARCH_LS1043A + default 2 + help + This is the divider that is used to derive QMAN clock from Platform + clock, in another word QMAN_clk = Platform_clk / this_divider. endmenu config RESV_RAM @@ -362,6 +524,20 @@ config RESV_RAM be at the high end of physical memory. The reserve RAM may be excluded from memory bank(s) passed to OS, or marked as reserved. +config SYS_FSL_EC1 + bool + help + Ethernet controller 1, this is connected to + MAC17 for LX2160A or to MAC3 for other SoCs + Provides DPAA2 capabilities + +config SYS_FSL_EC2 + bool + help + Ethernet controller 2, this is connected to + MAC18 for LX2160A or to MAC4 for other SoCs + Provides DPAA2 capabilities + config SYS_FSL_ERRATUM_A008336 bool @@ -386,13 +562,33 @@ config SYS_FSL_ERRATUM_A009660 config SYS_FSL_ERRATUM_A009929 bool + +config SYS_FSL_HAS_RGMII + bool + depends on SYS_FSL_EC1 || SYS_FSL_EC2 + + config SYS_MC_RSV_MEM_ALIGN hex "Management Complex reserved memory alignment" depends on RESV_RAM - default 0x20000000 + default 0x20000000 if ARCH_LS2080A || ARCH_LS1088A || ARCH_LX2160A help Reserved memory needs to be aligned for MC to use. Default value is 512MB. config SPL_LDSCRIPT default "arch/arm/cpu/armv8/u-boot-spl.lds" if ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A + +config HAS_FSL_XHCI_USB + bool + default y if ARCH_LS1043A || ARCH_LS1046A + help + For some SoC(such as LS1043A and LS1046A), USB and QE-HDLC multiplex use + pins, select it when the pins are assigned to USB. + +config TFABOOT + bool "Support for booting from TFA" + default n + help + Enabling this will make a U-Boot binary that is capable of being + booted via TFA.