X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=arch%2Farm%2Fcpu%2Farmv8%2Ffsl-layerscape%2FKconfig;h=1b98f5a95513a860c2d6d654934a69df0522e79a;hb=6500ec7a5a2a2a59128dba6f49d9905fc1258811;hp=ba411e2af85296bd3e54fc7c479bd2fd9936d6c5;hpb=0541527bde7d2df155fc9691115d234fa7a3f603;p=platform%2Fkernel%2Fu-boot.git diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index ba411e2..1b98f5a 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -5,6 +5,8 @@ config ARCH_LS1012A select SYS_FSL_DDR_BE select SYS_FSL_MMDC select SYS_FSL_ERRATUM_A010315 + select ARCH_EARLY_INIT_R + select BOARD_EARLY_INIT_F config ARCH_LS1043A bool @@ -22,6 +24,10 @@ config ARCH_LS1043A select SYS_FSL_ERRATUM_A010539 select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_DDR4 + select ARCH_EARLY_INIT_R + select BOARD_EARLY_INIT_F + imply SCSI + imply CMD_PCI config ARCH_LS1046A bool @@ -30,7 +36,9 @@ config ARCH_LS1046A select SYS_FSL_DDR select SYS_FSL_DDR_BE select SYS_FSL_DDR_VER_50 + select SYS_FSL_ERRATUM_A008336 select SYS_FSL_ERRATUM_A008511 + select SYS_FSL_ERRATUM_A008850 select SYS_FSL_ERRATUM_A009801 select SYS_FSL_ERRATUM_A009803 select SYS_FSL_ERRATUM_A009942 @@ -38,10 +46,17 @@ config ARCH_LS1046A select SYS_FSL_ERRATUM_A010539 select SYS_FSL_HAS_DDR4 select SYS_FSL_SRDS_2 + select ARCH_EARLY_INIT_R + select BOARD_EARLY_INIT_F + imply SCSI config ARCH_LS2080A bool select ARMV8_SET_SMPEN + select ARM_ERRATA_826974 + select ARM_ERRATA_828024 + select ARM_ERRATA_829520 + select ARM_ERRATA_833471 select FSL_LSCH3 select SYS_FSL_DDR select SYS_FSL_DDR_LE @@ -52,6 +67,8 @@ config ARCH_LS2080A select SYS_FSL_SEC_COMPAT_5 select SYS_FSL_SEC_LE select SYS_FSL_SRDS_2 + select FSL_TZASC_1 + select FSL_TZASC_2 select SYS_FSL_ERRATUM_A008336 select SYS_FSL_ERRATUM_A008511 select SYS_FSL_ERRATUM_A008514 @@ -62,6 +79,9 @@ config ARCH_LS2080A select SYS_FSL_ERRATUM_A009803 select SYS_FSL_ERRATUM_A009942 select SYS_FSL_ERRATUM_A010165 + select SYS_FSL_ERRATUM_A009203 + select ARCH_EARLY_INIT_R + select BOARD_EARLY_INIT_F config FSL_LSCH2 bool @@ -76,6 +96,14 @@ config FSL_LSCH3 select SYS_FSL_SRDS_1 select SYS_HAS_SERDES +config FSL_MC_ENET + bool "Management Complex network" + depends on ARCH_LS2080A + default y + select RESV_RAM + help + Enable Management Complex (MC) network + menu "Layerscape architecture" depends on FSL_LSCH2 || FSL_LSCH3 @@ -110,9 +138,24 @@ config FSL_LS_PPA which is loaded during boot stage, and then remains resident in RAM and runs in the TrustZone after boot. Say y to enable it. + +config SPL_FSL_LS_PPA + bool "FSL Layerscape PPA firmware support for SPL build" + depends on !ARMV8_PSCI + select SPL_ARMV8_SEC_FIRMWARE_SUPPORT + select SEC_FIRMWARE_ARMV8_PSCI + select ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT if FSL_LSCH2 + help + The FSL Primary Protected Application (PPA) is a software component + which is loaded during boot stage, and then remains resident in RAM + and runs in the TrustZone after boot. This is to load PPA during SPL + stage instead of the RAM version of U-Boot. Once PPA is initialized, + the rest of U-Boot (including RAM version) runs at EL2. choice prompt "FSL Layerscape PPA firmware loading-media select" depends on FSL_LS_PPA + default SYS_LS_PPA_FW_IN_MMC if SD_BOOT + default SYS_LS_PPA_FW_IN_NAND if NAND_BOOT default SYS_LS_PPA_FW_IN_XIP config SYS_LS_PPA_FW_IN_XIP @@ -121,18 +164,57 @@ config SYS_LS_PPA_FW_IN_XIP Say Y here if the PPA firmware locate at XIP flash, such as NOR or QSPI flash. +config SYS_LS_PPA_FW_IN_MMC + bool "eMMC or SD Card" + help + Say Y here if the PPA firmware locate at eMMC/SD card. + +config SYS_LS_PPA_FW_IN_NAND + bool "NAND" + help + Say Y here if the PPA firmware locate at NAND flash. + endchoice config SYS_LS_PPA_FW_ADDR hex "Address of PPA firmware loading from" depends on FSL_LS_PPA - default 0x40500000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT - default 0x60500000 if SYS_LS_PPA_FW_IN_XIP + default 0x20400000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT && ARCH_LS2080A + default 0x40400000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT + default 0x580400000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS2080A + default 0x60400000 if SYS_LS_PPA_FW_IN_XIP + default 0x400000 if SYS_LS_PPA_FW_IN_MMC + default 0x400000 if SYS_LS_PPA_FW_IN_NAND + help If the PPA firmware locate at XIP flash, such as NOR or QSPI flash, this address is a directly memory-mapped. If it is in a serial accessed flash, such as NAND and SD card, it is a byte offset. + +config SYS_LS_PPA_ESBC_ADDR + hex "hdr address of PPA firmware loading from" + depends on FSL_LS_PPA && CHAIN_OF_TRUST + default 0x600c0000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1043A + default 0x40740000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1046A + default 0x40480000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1012A + default 0x580c40000 if SYS_LS_PPA_FW_IN_XIP && FSL_LSCH3 + default 0x700000 if SYS_LS_PPA_FW_IN_MMC + default 0x700000 if SYS_LS_PPA_FW_IN_NAND + help + If the PPA header firmware locate at XIP flash, such as NOR or + QSPI flash, this address is a directly memory-mapped. + If it is in a serial accessed flash, such as NAND and SD + card, it is a byte offset. + +config LS_PPA_ESBC_HDR_SIZE + hex "Length of PPA ESBC header" + depends on FSL_LS_PPA && CHAIN_OF_TRUST && !SYS_LS_PPA_FW_IN_XIP + default 0x2000 + help + Length (in bytes) of PPA ESBC header to be copied from MMC/SD or + NAND to memory to validate PPA image. + endmenu config SYS_FSL_ERRATUM_A010315 @@ -185,6 +267,12 @@ config SYS_FSL_SRDS_2 config SYS_HAS_SERDES bool +config FSL_TZASC_1 + bool + +config FSL_TZASC_2 + bool + endmenu menu "Layerscape clock tree configuration" @@ -220,7 +308,7 @@ config SYS_FSL_DSPI_CLK_DIV default 2 help This is the divider that is used to derive DSPI clock from Platform - PLL, in another word DSPI_clk = Platform_PLL_freq / this_divider. + clock, in another word DSPI_clk = Platform_clk / this_divider. config SYS_FSL_DUART_CLK_DIV int "DUART clock divider" @@ -264,6 +352,16 @@ config SYS_FSL_SDHC_CLK_DIV clock, in another word SDHC_clk = Platform_clk / this_divider. endmenu +config RESV_RAM + bool + help + Reserve memory from the top, tracked by gd->arch.resv_ram. This + reserved RAM can be used by special driver that resides in memory + after U-Boot exits. It's up to implementation to allocate and allow + access to this reserved memory. For example, the reserved RAM can + be at the high end of physical memory. The reserve RAM may be + excluded from memory bank(s) passed to OS, or marked as reserved. + config SYS_FSL_ERRATUM_A008336 bool @@ -276,6 +374,9 @@ config SYS_FSL_ERRATUM_A008585 config SYS_FSL_ERRATUM_A008850 bool +config SYS_FSL_ERRATUM_A009203 + bool + config SYS_FSL_ERRATUM_A009635 bool @@ -284,3 +385,11 @@ config SYS_FSL_ERRATUM_A009660 config SYS_FSL_ERRATUM_A009929 bool + +config SYS_MC_RSV_MEM_ALIGN + hex "Management Complex reserved memory alignment" + depends on RESV_RAM + default 0x20000000 + help + Reserved memory needs to be aligned for MC to use. Default value + is 512MB.