X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=arch%2Farm%2Fcpu%2Farmv7%2Fomap4%2Fhw_data.c;h=4dec73e9ec23627b5de4f687e2b6ed6b60095337;hb=e97f9d817e600cd6f43d1d0da76f5787e33a5c56;hp=7551b9861ee68d1daf7051ac58812b276c1688dd;hpb=76b40ab41eff1f402ee52ba768b09daad293b9bb;p=platform%2Fkernel%2Fu-boot.git diff --git a/arch/arm/cpu/armv7/omap4/hw_data.c b/arch/arm/cpu/armv7/omap4/hw_data.c index 7551b98..4dec73e 100644 --- a/arch/arm/cpu/armv7/omap4/hw_data.c +++ b/arch/arm/cpu/armv7/omap4/hw_data.c @@ -7,29 +7,13 @@ * * Sricharan R * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * SPDX-License-Identifier: GPL-2.0+ */ #include #include #include #include -#include +#include #include #include @@ -40,7 +24,7 @@ struct dplls const **dplls_data = struct vcores_data const **omap_vcores = (struct vcores_data const **) OMAP_SRAM_SCRATCH_VCORES_PTR; struct omap_sys_ctrl_regs const **ctrl = - (struct omap_sys_ctrl_regs const **)OMAP4_SRAM_SCRATCH_SYS_CTRL; + (struct omap_sys_ctrl_regs const **)OMAP_SRAM_SCRATCH_SYS_CTRL; /* * The M & N values in the following tables are created using the @@ -66,6 +50,7 @@ static const struct dpll_params mpu_dpll_params_1400mhz[NUM_SYS_CLKS] = { /* * dpll locked at 1600 MHz - MPU clk at 800 MHz(OPP Turbo 4430) * OMAP4430 OPP_TURBO frequency + * OMAP4470 OPP_NOM frequency */ static const struct dpll_params mpu_dpll_params_1600mhz[NUM_SYS_CLKS] = { {200, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ @@ -92,6 +77,7 @@ static const struct dpll_params mpu_dpll_params_1200mhz[NUM_SYS_CLKS] = { }; /* OMAP4460 OPP_NOM frequency */ +/* OMAP4470 OPP_NOM (Low Power) frequency */ static const struct dpll_params core_dpll_params_1600mhz[NUM_SYS_CLKS] = { {200, 2, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 12 MHz */ {800, 12, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 13 MHz */ @@ -214,18 +200,39 @@ struct dplls omap4460_dplls = { .ddr = NULL }; +struct dplls omap4470_dplls = { + .mpu = mpu_dpll_params_1600mhz, + .core = core_dpll_params_1600mhz, + .per = per_dpll_params_1536mhz, + .iva = iva_dpll_params_1862mhz, +#ifdef CONFIG_SYS_OMAP_ABE_SYSCK + .abe = abe_dpll_params_sysclk_196608khz, +#else + .abe = &abe_dpll_params_32k_196608khz, +#endif + .usb = usb_dpll_params_1920mhz, + .ddr = NULL +}; + struct pmic_data twl6030_4430es1 = { .base_offset = PHOENIX_SMPS_BASE_VOLT_STD_MODE_UV, - .step = 12660, /* 10 mV represented in uV */ + .step = 12660, /* 12.66 mV represented in uV */ /* The code starts at 1 not 0 */ .start_code = 1, + .i2c_slave_addr = SMPS_I2C_SLAVE_ADDR, + .pmic_bus_init = sri2c_init, + .pmic_write = omap_vc_bypass_send_value, }; +/* twl6030 struct is used for TWL6030 and TWL6032 PMIC */ struct pmic_data twl6030 = { .base_offset = PHOENIX_SMPS_BASE_VOLT_STD_MODE_WITH_OFFSET_UV, - .step = 12660, /* 10 mV represented in uV */ + .step = 12660, /* 12.66 mV represented in uV */ /* The code starts at 1 not 0 */ .start_code = 1, + .i2c_slave_addr = SMPS_I2C_SLAVE_ADDR, + .pmic_bus_init = sri2c_init, + .pmic_write = omap_vc_bypass_send_value, }; struct pmic_data tps62361 = { @@ -233,7 +240,10 @@ struct pmic_data tps62361 = { .step = 10000, /* 10 mV represented in uV */ .start_code = 0, .gpio = TPS62361_VSEL0_GPIO, - .gpio_en = 1 + .gpio_en = 1, + .i2c_slave_addr = SMPS_I2C_SLAVE_ADDR, + .pmic_bus_init = sri2c_init, + .pmic_write = omap_vc_bypass_send_value, }; struct vcores_data omap4430_volts_es1 = { @@ -271,11 +281,29 @@ struct vcores_data omap4460_volts = { .core.value = 1200, .core.addr = SMPS_REG_ADDR_VCORE1, - .core.pmic = &tps62361, + .core.pmic = &twl6030, .mm.value = 1200, .mm.addr = SMPS_REG_ADDR_VCORE2, - .mm.pmic = &tps62361, + .mm.pmic = &twl6030, +}; + +/* + * Take closest integer part of the mV value corresponding to a TWL6032 SMPS + * voltage selection code. Aligned with OMAP4470 ES1.0 OCA V.0.7. + */ +struct vcores_data omap4470_volts = { + .mpu.value = 1202, + .mpu.addr = SMPS_REG_ADDR_SMPS1, + .mpu.pmic = &twl6030, + + .core.value = 1126, + .core.addr = SMPS_REG_ADDR_SMPS2, + .core.pmic = &twl6030, + + .mm.value = 1139, + .mm.addr = SMPS_REG_ADDR_SMPS5, + .mm.pmic = &twl6030, }; /* @@ -371,91 +399,6 @@ void enable_basic_uboot_clocks(void) 1); } -/* - * Enable non-essential clock domains, modules and - * do some additional special settings needed - */ -void enable_non_essential_clocks(void) -{ - u32 const clk_domains_non_essential[] = { - (*prcm)->cm_mpu_m3_clkstctrl, - (*prcm)->cm_ivahd_clkstctrl, - (*prcm)->cm_dsp_clkstctrl, - (*prcm)->cm_dss_clkstctrl, - (*prcm)->cm_sgx_clkstctrl, - (*prcm)->cm1_abe_clkstctrl, - (*prcm)->cm_c2c_clkstctrl, - (*prcm)->cm_cam_clkstctrl, - (*prcm)->cm_dss_clkstctrl, - (*prcm)->cm_sdma_clkstctrl, - 0 - }; - - u32 const clk_modules_hw_auto_non_essential[] = { - (*prcm)->cm_l3instr_l3_3_clkctrl, - (*prcm)->cm_l3instr_l3_instr_clkctrl, - (*prcm)->cm_l3instr_intrconn_wp1_clkctrl, - (*prcm)->cm_l3init_hsi_clkctrl, - 0 - }; - - u32 const clk_modules_explicit_en_non_essential[] = { - (*prcm)->cm1_abe_aess_clkctrl, - (*prcm)->cm1_abe_pdm_clkctrl, - (*prcm)->cm1_abe_dmic_clkctrl, - (*prcm)->cm1_abe_mcasp_clkctrl, - (*prcm)->cm1_abe_mcbsp1_clkctrl, - (*prcm)->cm1_abe_mcbsp2_clkctrl, - (*prcm)->cm1_abe_mcbsp3_clkctrl, - (*prcm)->cm1_abe_slimbus_clkctrl, - (*prcm)->cm1_abe_timer5_clkctrl, - (*prcm)->cm1_abe_timer6_clkctrl, - (*prcm)->cm1_abe_timer7_clkctrl, - (*prcm)->cm1_abe_timer8_clkctrl, - (*prcm)->cm1_abe_wdt3_clkctrl, - (*prcm)->cm_l4per_gptimer9_clkctrl, - (*prcm)->cm_l4per_gptimer10_clkctrl, - (*prcm)->cm_l4per_gptimer11_clkctrl, - (*prcm)->cm_l4per_gptimer3_clkctrl, - (*prcm)->cm_l4per_gptimer4_clkctrl, - (*prcm)->cm_l4per_hdq1w_clkctrl, - (*prcm)->cm_l4per_mcbsp4_clkctrl, - (*prcm)->cm_l4per_mcspi2_clkctrl, - (*prcm)->cm_l4per_mcspi3_clkctrl, - (*prcm)->cm_l4per_mcspi4_clkctrl, - (*prcm)->cm_l4per_mmcsd3_clkctrl, - (*prcm)->cm_l4per_mmcsd4_clkctrl, - (*prcm)->cm_l4per_mmcsd5_clkctrl, - (*prcm)->cm_l4per_uart1_clkctrl, - (*prcm)->cm_l4per_uart2_clkctrl, - (*prcm)->cm_l4per_uart4_clkctrl, - (*prcm)->cm_wkup_keyboard_clkctrl, - (*prcm)->cm_wkup_wdtimer2_clkctrl, - (*prcm)->cm_cam_iss_clkctrl, - (*prcm)->cm_cam_fdif_clkctrl, - (*prcm)->cm_dss_dss_clkctrl, - (*prcm)->cm_sgx_sgx_clkctrl, - 0 - }; - - /* Enable optional functional clock for ISS */ - setbits_le32((*prcm)->cm_cam_iss_clkctrl, ISS_CLKCTRL_OPTFCLKEN_MASK); - - /* Enable all optional functional clocks of DSS */ - setbits_le32((*prcm)->cm_dss_dss_clkctrl, DSS_CLKCTRL_OPTFCLKEN_MASK); - - do_enable_clocks(clk_domains_non_essential, - clk_modules_hw_auto_non_essential, - clk_modules_explicit_en_non_essential, - 0); - - /* Put camera module in no sleep mode */ - clrsetbits_le32((*prcm)->cm_cam_clkstctrl, - MODULE_CLKCTRL_MODULEMODE_MASK, - CD_CLKCTRL_CLKTRCTRL_NO_SLEEP << - MODULE_CLKCTRL_MODULEMODE_SHIFT); -} - void hw_data_init(void) { u32 omap_rev = omap_revision(); @@ -483,6 +426,11 @@ void hw_data_init(void) *omap_vcores = &omap4460_volts; break; + case OMAP4470_ES1_0: + *dplls_data = &omap4470_dplls; + *omap_vcores = &omap4470_volts; + break; + default: printf("\n INVALID OMAP REVISION "); }