X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=arch%2Farm%2Fcpu%2Farmv7%2Fomap3%2Fboard.c;h=f3cd81ad98879b05b55bab3017b22f71b4bffe4b;hb=6acc7c3cbc05873d62118640cf964e9c9665804c;hp=cdf452dfbc7d346dd4e89e0809e5e772caab953f;hpb=a67fe5f284c73e5171b80657619ee24d7cc9726b;p=platform%2Fkernel%2Fu-boot.git

diff --git a/arch/arm/cpu/armv7/omap3/board.c b/arch/arm/cpu/armv7/omap3/board.c
index cdf452d..f3cd81a 100644
--- a/arch/arm/cpu/armv7/omap3/board.c
+++ b/arch/arm/cpu/armv7/omap3/board.c
@@ -33,6 +33,7 @@
  * MA 02111-1307 USA
  */
 #include <common.h>
+#include <spl.h>
 #include <asm/io.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/arch/mem.h>
@@ -40,11 +41,18 @@
 #include <asm/armv7.h>
 #include <asm/arch/gpio.h>
 #include <asm/omap_common.h>
+#include <asm/arch/mmc_host_def.h>
+#include <i2c.h>
+#include <linux/compiler.h>
+
+DECLARE_GLOBAL_DATA_PTR;
 
 /* Declarations */
 extern omap3_sysinfo sysinfo;
 static void omap3_setup_aux_cr(void);
+#ifndef CONFIG_SYS_L2CACHE_OFF
 static void omap3_invalidate_l2_cache_secure(void);
+#endif
 
 static const struct gpio_bank gpio_bank_34xx[6] = {
 	{ (void *)OMAP34XX_GPIO1_BASE, METHOD_GPIO_24XX },
@@ -67,28 +75,48 @@ const struct gpio_bank *const omap_gpio_bank = gpio_bank_34xx;
 u32 omap3_boot_device = BOOT_DEVICE_NAND;
 
 /* auto boot mode detection is not possible for OMAP3 - hard code */
-u32 omap_boot_mode(void)
+u32 spl_boot_mode(void)
 {
-	switch (omap_boot_device()) {
+	switch (spl_boot_device()) {
 	case BOOT_DEVICE_MMC2:
 		return MMCSD_MODE_RAW;
 	case BOOT_DEVICE_MMC1:
 		return MMCSD_MODE_FAT;
 		break;
-	case BOOT_DEVICE_NAND:
-		return NAND_MODE_HW_ECC;
-		break;
 	default:
 		puts("spl: ERROR:  unknown device - can't select boot mode\n");
 		hang();
 	}
 }
 
-u32 omap_boot_device(void)
+u32 spl_boot_device(void)
 {
 	return omap3_boot_device;
 }
 
+int board_mmc_init(bd_t *bis)
+{
+	switch (spl_boot_device()) {
+	case BOOT_DEVICE_MMC1:
+		omap_mmc_init(0, 0, 0);
+		break;
+	case BOOT_DEVICE_MMC2:
+	case BOOT_DEVICE_MMC2_2:
+		omap_mmc_init(1, 0, 0);
+		break;
+	}
+	return 0;
+}
+
+void spl_board_init(void)
+{
+#ifdef CONFIG_SPL_NAND_SUPPORT
+	gpmc_init();
+#endif
+#ifdef CONFIG_SPL_I2C_SUPPORT
+	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+#endif
+}
 #endif /* CONFIG_SPL_BUILD */
 
 
@@ -139,7 +167,7 @@ void secureworld_exit()
 {
 	unsigned long i;
 
-	/* configrue non-secure access control register */
+	/* configure non-secure access control register */
 	__asm__ __volatile__("mrc p15, 0, %0, c1, c1, 2":"=r"(i));
 	/* enabling co-processor CP10 and CP11 accesses in NS world */
 	__asm__ __volatile__("orr %0, %0, #0xC00":"=r"(i));
@@ -223,14 +251,33 @@ void s_init(void)
 
 	per_clocks_enable();
 
+#ifdef CONFIG_USB_EHCI_OMAP
+	ehci_clocks_enable();
+#endif
+
 #ifdef CONFIG_SPL_BUILD
+	gd = &gdata;
+
 	preloader_console_init();
+
+	timer_init();
 #endif
 
 	if (!in_sdram)
 		mem_init();
 }
 
+/*
+ * Routine: misc_init_r
+ * Description: A basic misc_init_r that just displays the die ID
+ */
+int __weak misc_init_r(void)
+{
+	dieid_num_r();
+
+	return 0;
+}
+
 /******************************************************************************
  * Routine: wait_for_command_complete
  * Description: Wait for posting to finish on watchdog
@@ -365,6 +412,19 @@ static void omap3_update_aux_cr_secure(u32 set_bits, u32 clear_bits)
 	}
 }
 
+static void omap3_setup_aux_cr(void)
+{
+	/* Workaround for Cortex-A8 errata: #454179 #430973
+	 *	Set "IBE" bit
+	 *	Set "Disable Branch Size Mispredicts" bit
+	 * Workaround for erratum #621766
+	 *	Enable L1NEON bit
+	 * ACR |= (IBE | DBSM | L1NEON) => ACR |= 0xE0
+	 */
+	omap3_update_aux_cr_secure(0xE0, 0);
+}
+
+#ifndef CONFIG_SYS_L2CACHE_OFF
 static void omap3_update_aux_cr(u32 set_bits, u32 clear_bits)
 {
 	u32 acr;
@@ -378,19 +438,6 @@ static void omap3_update_aux_cr(u32 set_bits, u32 clear_bits)
 	asm volatile ("mcr p15, 0, %0, c1, c0, 1" : : "r" (acr));
 }
 
-static void omap3_setup_aux_cr(void)
-{
-	/* Workaround for Cortex-A8 errata: #454179 #430973
-	 *	Set "IBE" bit
-	 *	Set "Disable Brach Size Mispredicts" bit
-	 * Workaround for erratum #621766
-	 *	Enable L1NEON bit
-	 * ACR |= (IBE | DBSM | L1NEON) => ACR |= 0xE0
-	 */
-	omap3_update_aux_cr_secure(0xE0, 0);
-}
-
-#ifndef CONFIG_SYS_L2CACHE_OFF
 /* Invalidate the entire L2 cache from secure mode */
 static void omap3_invalidate_l2_cache_secure(void)
 {
@@ -419,7 +466,7 @@ void v7_outer_cache_enable(void)
 	omap3_update_aux_cr(0x2, 0);
 }
 
-void v7_outer_cache_disable(void)
+void omap3_outer_cache_disable(void)
 {
 	/* Clear L2EN */
 	omap3_update_aux_cr_secure(0, 0x2);