X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=arch%2Farm%2Fcpu%2Farmv7%2Fomap3%2Fboard.c;h=0c44ea53e12ed34df596abb5ed0f285f273b0b2b;hb=a69fdc7787bfa2f27eed74c2ee58c28ce932d502;hp=b72fadc2575a4f4facc2affe4c0319e8de73a4af;hpb=345be0b26734c560e8b33531ab21a1272179c5c3;p=platform%2Fkernel%2Fu-boot.git diff --git a/arch/arm/cpu/armv7/omap3/board.c b/arch/arm/cpu/armv7/omap3/board.c index b72fadc..0c44ea5 100644 --- a/arch/arm/cpu/armv7/omap3/board.c +++ b/arch/arm/cpu/armv7/omap3/board.c @@ -14,111 +14,61 @@ * Syed Mohammed Khasim * * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * SPDX-License-Identifier: GPL-2.0+ */ #include +#include #include #include #include #include #include #include -#include +#include #include -#include -#include #include DECLARE_GLOBAL_DATA_PTR; /* Declarations */ extern omap3_sysinfo sysinfo; -static void omap3_setup_aux_cr(void); #ifndef CONFIG_SYS_L2CACHE_OFF static void omap3_invalidate_l2_cache_secure(void); #endif -static const struct gpio_bank gpio_bank_34xx[6] = { - { (void *)OMAP34XX_GPIO1_BASE, METHOD_GPIO_24XX }, - { (void *)OMAP34XX_GPIO2_BASE, METHOD_GPIO_24XX }, - { (void *)OMAP34XX_GPIO3_BASE, METHOD_GPIO_24XX }, - { (void *)OMAP34XX_GPIO4_BASE, METHOD_GPIO_24XX }, - { (void *)OMAP34XX_GPIO5_BASE, METHOD_GPIO_24XX }, - { (void *)OMAP34XX_GPIO6_BASE, METHOD_GPIO_24XX }, +#ifdef CONFIG_DM_GPIO +static const struct omap_gpio_platdata omap34xx_gpio[] = { + { 0, OMAP34XX_GPIO1_BASE }, + { 1, OMAP34XX_GPIO2_BASE }, + { 2, OMAP34XX_GPIO3_BASE }, + { 3, OMAP34XX_GPIO4_BASE }, + { 4, OMAP34XX_GPIO5_BASE }, + { 5, OMAP34XX_GPIO6_BASE }, }; -const struct gpio_bank *const omap_gpio_bank = gpio_bank_34xx; +U_BOOT_DEVICES(am33xx_gpios) = { + { "gpio_omap", &omap34xx_gpio[0] }, + { "gpio_omap", &omap34xx_gpio[1] }, + { "gpio_omap", &omap34xx_gpio[2] }, + { "gpio_omap", &omap34xx_gpio[3] }, + { "gpio_omap", &omap34xx_gpio[4] }, + { "gpio_omap", &omap34xx_gpio[5] }, +}; -#ifdef CONFIG_SPL_BUILD -/* -* We use static variables because global data is not ready yet. -* Initialized data is available in SPL right from the beginning. -* We would not typically need to save these parameters in regular -* U-Boot. This is needed only in SPL at the moment. -*/ -u32 omap3_boot_device = BOOT_DEVICE_NAND; - -/* auto boot mode detection is not possible for OMAP3 - hard code */ -u32 spl_boot_mode(void) -{ - switch (spl_boot_device()) { - case BOOT_DEVICE_MMC2: - return MMCSD_MODE_RAW; - case BOOT_DEVICE_MMC1: - return MMCSD_MODE_FAT; - break; - default: - puts("spl: ERROR: unknown device - can't select boot mode\n"); - hang(); - } -} +#else -u32 spl_boot_device(void) -{ - return omap3_boot_device; -} +static const struct gpio_bank gpio_bank_34xx[6] = { + { (void *)OMAP34XX_GPIO1_BASE }, + { (void *)OMAP34XX_GPIO2_BASE }, + { (void *)OMAP34XX_GPIO3_BASE }, + { (void *)OMAP34XX_GPIO4_BASE }, + { (void *)OMAP34XX_GPIO5_BASE }, + { (void *)OMAP34XX_GPIO6_BASE }, +}; -int board_mmc_init(bd_t *bis) -{ - switch (spl_boot_device()) { - case BOOT_DEVICE_MMC1: - omap_mmc_init(0, 0, 0, -1, -1); - break; - case BOOT_DEVICE_MMC2: - case BOOT_DEVICE_MMC2_2: - omap_mmc_init(1, 0, 0, -1, -1); - break; - } - return 0; -} +const struct gpio_bank *const omap_gpio_bank = gpio_bank_34xx; -void spl_board_init(void) -{ -#if defined(CONFIG_SPL_NAND_SUPPORT) || defined(CONFIG_SPL_ONENAND_SUPPORT) - gpmc_init(); -#endif -#ifdef CONFIG_SPL_I2C_SUPPORT - i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); #endif -} -#endif /* CONFIG_SPL_BUILD */ - /****************************************************************************** * Routine: secure_unlock @@ -163,7 +113,7 @@ void secure_unlock_mem(void) * configure secure registers and exit secure world * general use. *****************************************************************************/ -void secureworld_exit() +void secureworld_exit(void) { unsigned long i; @@ -194,7 +144,7 @@ void secureworld_exit() * Description: If chip is GP/EMU(special) type, unlock the SRAM for * general use. *****************************************************************************/ -void try_unlock_memory() +void try_unlock_memory(void) { int mode; int in_sdram = is_running_in_sdram(); @@ -230,15 +180,10 @@ void try_unlock_memory() *****************************************************************************/ void s_init(void) { - int in_sdram = is_running_in_sdram(); - watchdog_init(); try_unlock_memory(); - /* Errata workarounds */ - omap3_setup_aux_cr(); - #ifndef CONFIG_SYS_L2CACHE_OFF /* Invalidate L2-cache from secure mode */ omap3_invalidate_l2_cache_secure(); @@ -254,18 +199,14 @@ void s_init(void) #ifdef CONFIG_USB_EHCI_OMAP ehci_clocks_enable(); #endif +} #ifdef CONFIG_SPL_BUILD - gd = &gdata; - - preloader_console_init(); - - timer_init(); -#endif - - if (!in_sdram) - mem_init(); +void board_init_f(ulong dummy) +{ + mem_init(); } +#endif /* * Routine: misc_init_r @@ -273,7 +214,7 @@ void s_init(void) */ int __weak misc_init_r(void) { - dieid_num_r(); + omap_die_id_display(); return 0; } @@ -282,7 +223,7 @@ int __weak misc_init_r(void) * Routine: wait_for_command_complete * Description: Wait for posting to finish on watchdog *****************************************************************************/ -void wait_for_command_complete(struct watchdog *wd_base) +static void wait_for_command_complete(struct watchdog *wd_base) { int pending = 1; do { @@ -306,8 +247,8 @@ void watchdog_init(void) * should not be running and does not generate a PRCM reset. */ - sr32(&prcm_base->fclken_wkup, 5, 1, 1); - sr32(&prcm_base->iclken_wkup, 5, 1, 1); + setbits_le32(&prcm_base->fclken_wkup, 0x20); + setbits_le32(&prcm_base->iclken_wkup, 0x20); wait_on_value(ST_WDT2, 0x20, &prcm_base->idlest_wkup, 5); writel(WD_UNLOCK1, &wd2_base->wspr); @@ -343,7 +284,16 @@ static int do_switch_ecc(cmd_tbl_t * cmdtp, int flag, int argc, char * const arg goto usage; } } else if (strncmp(argv[1], "sw", 2) == 0) { - omap_nand_switch_ecc(0, 0); + if (argc == 2) { + omap_nand_switch_ecc(0, 1); + } else { + if (strncmp(argv[2], "hamming", 7) == 0) + omap_nand_switch_ecc(0, 1); + else if (strncmp(argv[2], "bch8", 4) == 0) + omap_nand_switch_ecc(0, 8); + else + goto usage; + } } else { goto usage; } @@ -406,39 +356,30 @@ static void omap3_emu_romcode_call(u32 service_id, u32 *parameters) do_omap3_emu_romcode_call(service_id, OMAP3_PUBLIC_SRAM_SCRATCH_AREA); } -static void omap3_update_aux_cr_secure(u32 set_bits, u32 clear_bits) +void __weak omap3_set_aux_cr_secure(u32 acr) { - u32 acr; - - /* Read ACR */ - asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr)); - acr &= ~clear_bits; - acr |= set_bits; + struct emu_hal_params emu_romcode_params; - if (get_device_type() == GP_DEVICE) { - omap3_gp_romcode_call(OMAP3_GP_ROMCODE_API_WRITE_ACR, - acr); - } else { - struct emu_hal_params emu_romcode_params; - emu_romcode_params.num_params = 1; - emu_romcode_params.param1 = acr; - omap3_emu_romcode_call(OMAP3_EMU_HAL_API_WRITE_ACR, - (u32 *)&emu_romcode_params); - } + emu_romcode_params.num_params = 1; + emu_romcode_params.param1 = acr; + omap3_emu_romcode_call(OMAP3_EMU_HAL_API_WRITE_ACR, + (u32 *)&emu_romcode_params); } -static void omap3_setup_aux_cr(void) +void v7_arch_cp15_set_acr(u32 acr, u32 cpu_midr, u32 cpu_rev_comb, + u32 cpu_variant, u32 cpu_rev) { - /* Workaround for Cortex-A8 errata: #454179 #430973 - * Set "IBE" bit - * Set "Disable Branch Size Mispredicts" bit - * Workaround for erratum #621766 - * Enable L1NEON bit - * ACR |= (IBE | DBSM | L1NEON) => ACR |= 0xE0 - */ - omap3_update_aux_cr_secure(0xE0, 0); + /* Write ACR - affects secure banked bits */ + if (get_device_type() == GP_DEVICE) + omap_smc1(OMAP3_GP_ROMCODE_API_WRITE_ACR, acr); + else + omap3_set_aux_cr_secure(acr); + + /* Write ACR - affects non-secure banked bits - some erratas need it */ + asm volatile ("mcr p15, 0, %0, c1, c0, 1" : : "r" (acr)); } + #ifndef CONFIG_SYS_L2CACHE_OFF static void omap3_update_aux_cr(u32 set_bits, u32 clear_bits) { @@ -448,17 +389,15 @@ static void omap3_update_aux_cr(u32 set_bits, u32 clear_bits) asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr)); acr &= ~clear_bits; acr |= set_bits; + v7_arch_cp15_set_acr(acr, 0, 0, 0, 0); - /* Write ACR - affects non-secure banked bits */ - asm volatile ("mcr p15, 0, %0, c1, c0, 1" : : "r" (acr)); } /* Invalidate the entire L2 cache from secure mode */ static void omap3_invalidate_l2_cache_secure(void) { if (get_device_type() == GP_DEVICE) { - omap3_gp_romcode_call(OMAP3_GP_ROMCODE_API_L2_INVAL, - 0); + omap_smc1(OMAP3_GP_ROMCODE_API_L2_INVAL, 0); } else { struct emu_hal_params emu_romcode_params; emu_romcode_params.num_params = 1; @@ -470,10 +409,9 @@ static void omap3_invalidate_l2_cache_secure(void) void v7_outer_cache_enable(void) { - /* Set L2EN */ - omap3_update_aux_cr_secure(0x2, 0); /* + * Set L2EN * On some revisions L2EN bit is banked on some revisions it's not * No harm in setting both banked bits(in fact this is required * by an erratum) @@ -483,10 +421,8 @@ void v7_outer_cache_enable(void) void omap3_outer_cache_disable(void) { - /* Clear L2EN */ - omap3_update_aux_cr_secure(0, 0x2); - /* + * Clear L2EN * On some revisions L2EN bit is banked on some revisions it's not * No harm in clearing both banked bits(in fact this is required * by an erratum) @@ -494,11 +430,3 @@ void omap3_outer_cache_disable(void) omap3_update_aux_cr(0, 0x2); } #endif /* !CONFIG_SYS_L2CACHE_OFF */ - -#ifndef CONFIG_SYS_DCACHE_OFF -void enable_caches(void) -{ - /* Enable D-cache. I-cache is already enabled in start.S */ - dcache_enable(); -} -#endif /* !CONFIG_SYS_DCACHE_OFF */