X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=arch%2Farm%2Fcpu%2Farmv7%2Fls102xa%2FKconfig;h=e75a895e0086c71ebe9a1dec09ff3d97e4051781;hb=46b5c8ed017958fc387ab86c71ae6c90abb6793c;hp=28bf778d9ce491a3cadc9301aeb7321f158f7fe7;hpb=c14d4b0051df5f569fa33d9937af1db267ed6d34;p=platform%2Fkernel%2Fu-boot.git

diff --git a/arch/arm/cpu/armv7/ls102xa/Kconfig b/arch/arm/cpu/armv7/ls102xa/Kconfig
index 28bf778..e75a895 100644
--- a/arch/arm/cpu/armv7/ls102xa/Kconfig
+++ b/arch/arm/cpu/armv7/ls102xa/Kconfig
@@ -1,21 +1,40 @@
 config ARCH_LS1021A
 	bool
+	select FSL_IFC if !QSPI_BOOT && !SD_BOOT_QSPI
+	select SYS_FSL_DDR_BE if SYS_FSL_DDR
+	select SYS_FSL_DDR_VER_50 if SYS_FSL_DDR
+	select SYS_FSL_IFC_BE
+	select SYS_FSL_ERRATUM_A008378
+	select SYS_FSL_ERRATUM_A008407
+	select SYS_FSL_ERRATUM_A008850 if SYS_FSL_DDR
+	select SYS_FSL_ERRATUM_A008997 if USB
+	select SYS_FSL_ERRATUM_A009008 if USB
+	select SYS_FSL_ERRATUM_A009663
+	select SYS_FSL_ERRATUM_A009798 if USB
+	select SYS_FSL_ERRATUM_A009942
 	select SYS_FSL_ERRATUM_A010315
+	select SYS_FSL_ESDHC_BE
+	select SYS_FSL_HAS_CCI400
+	select SYS_FSL_HAS_DDR3 if SYS_FSL_DDR
+	select SYS_FSL_HAS_DDR4 if SYS_FSL_DDR
+	select SYS_FSL_HAS_SEC
+	select SYS_FSL_SEC_COMPAT_5
+	select SYS_FSL_SEC_LE
 	select SYS_FSL_SRDS_1
 	select SYS_HAS_SERDES
-	select SYS_FSL_DDR_BE
-	select SYS_FSL_DDR_VER_50
+	select SYS_I2C_MXC
+	imply CMD_PCI
+	imply SCSI
+	imply SCSI_AHCI
 
 menu "LS102xA architecture"
 	depends on ARCH_LS1021A
 
 config LS1_DEEP_SLEEP
 	bool "Deep sleep"
-	depends on ARCH_LS1021A
 
 config MAX_CPUS
 	int "Maximum number of CPUs permitted for LS102xA"
-	depends on ARCH_LS1021A
 	default 2
 	help
 	  Set this number to the maximum number of possible CPUs in the SoC.
@@ -24,66 +43,59 @@ config MAX_CPUS
 	  cores, count the reserved ports. This will allocate enough memory
 	  in spin table to properly handle all cores.
 
-config NUM_DDR_CONTROLLERS
-	int "Maximum DDR controllers"
-	default 1
-
-config SYS_FSL_ERRATUM_A010315
-	bool "Workaround for PCIe erratum A010315"
+config SYS_CCI400_OFFSET
+	hex "Offset for CCI400 base"
+	depends on SYS_FSL_HAS_CCI400
+	default 0x180000
+	help
+	  Offset for CCI400 base.
+	  CCI400 base addr = CCSRBAR + CCI400_OFFSET
 
-config SYS_FSL_SRDS_1
+config SYS_FSL_ERRATUM_A008850
 	bool
+	help
+	  Workaround for DDR erratum A008850
 
-config SYS_FSL_SRDS_2
+config SYS_FSL_ERRATUM_A008997
 	bool
+	help
+	  Workaround for USB PHY erratum A008997
 
-config SYS_HAS_SERDES
+config SYS_FSL_ERRATUM_A009007
 	bool
+	help
+	  Workaround for USB PHY erratum A009007
 
-config SYS_FSL_DDR
-	bool "Freescale DDR driver"
+config SYS_FSL_ERRATUM_A009008
+	bool
 	help
-	  Select Freescale General DDR driver, shared between most Freescale
-	  PowerPC- based SoCs (such as mpc83xx, mpc85xx, mpc86xx) and ARM-
-	  based Layerscape SoCs (such as ls2080a).
+	  Workaround for USB PHY erratum A009008
 
-config SYS_FSL_DDR_BE
+config SYS_FSL_ERRATUM_A009798
 	bool
-	default y
 	help
-	  Access DDR registers in big-endian.
+	  Workaround for USB PHY erratum A009798
 
-config SYS_FSL_DDR_VER
-	int
-	default 50 if SYS_FSL_DDR_VER_50
+config SYS_FSL_ERRATUM_A010315
+	bool "Workaround for PCIe erratum A010315"
 
-config SYS_FSL_DDR_VER_50
+config SYS_FSL_HAS_CCI400
 	bool
 
-config SYS_FSL_DDRC_ARM_GEN3
+config SYS_FSL_SRDS_1
 	bool
 
-config SYS_FSL_DDRC_GEN4
+config SYS_FSL_SRDS_2
 	bool
 
-config SYS_FSL_DDR3
-	bool "Freescale DDR3 controller"
-	depends on !SYS_FSL_DDR4
-	select SYS_FSL_DDR
-	select SYS_FSL_DDRC_ARM_GEN3
-	help
-	  Enable Freescale DDR3 controller on ARM-based SoCs.
-
-config SYS_FSL_DDR4
-	bool "Freescale DDR4 controller"
-	select SYS_FSL_DDR
-	select SYS_FSL_DDRC_GEN4
-	help
-	  Enable Freescale DDR4 controller.
+config SYS_HAS_SERDES
+	bool
 
 config SYS_FSL_IFC_BANK_COUNT
 	int "Maximum banks of Integrated flash controller"
-	depends on ARCH_LS1021A
 	default 8
 
+config SYS_FSL_ERRATUM_A008407
+	bool
+
 endmenu