X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=arch%2Farm%2Fcpu%2Farm926ejs%2Fdavinci%2Fet1011c.c;h=df35e44d138aca279688cf297555f2cf2708fcfc;hb=fb1d6332b5430b90a8fa8ebab709f33a60e9f816;hp=da073457a30a5092f352c19176cc622facdd8f4d;hpb=062fe7d332c28ede25626f448681e43d76bb312e;p=platform%2Fkernel%2Fu-boot.git

diff --git a/arch/arm/cpu/arm926ejs/davinci/et1011c.c b/arch/arm/cpu/arm926ejs/davinci/et1011c.c
index da07345..df35e44 100644
--- a/arch/arm/cpu/arm926ejs/davinci/et1011c.c
+++ b/arch/arm/cpu/arm926ejs/davinci/et1011c.c
@@ -39,11 +39,9 @@ int et1011c_get_link_speed(int phy_addr)
 	u_int16_t	data;
 
 	if (davinci_eth_phy_read(phy_addr, MII_STATUS_REG, &data) && (data & 0x04)) {
-		davinci_eth_phy_read(EMAC_MDIO_PHY_NUM,
-				MII_PHY_CONFIG_REG, &data);
+		davinci_eth_phy_read(phy_addr, MII_PHY_CONFIG_REG, &data);
 		/* Enable 125MHz clock sourced from PHY */
-		davinci_eth_phy_write(EMAC_MDIO_PHY_NUM,
-			MII_PHY_CONFIG_REG,
+		davinci_eth_phy_write(phy_addr, MII_PHY_CONFIG_REG,
 			data | PHY_SYS_CLK_EN);
 		return (1);
 	}