X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=arch%2FKconfig.nxp;h=8c5a6f63a9a5873367791e5238cd5b61752cd2d6;hb=e9dcd5b40236b82672117464564d38511f1f7a0b;hp=ccbf684bdb36e997ec069213b6ee7c2ad4890eb6;hpb=5aad0a14bacc22b9d36956f12fa9480e3c0c672f;p=platform%2Fkernel%2Fu-boot.git

diff --git a/arch/Kconfig.nxp b/arch/Kconfig.nxp
index ccbf684..8c5a6f6 100644
--- a/arch/Kconfig.nxp
+++ b/arch/Kconfig.nxp
@@ -16,6 +16,7 @@ config CHAIN_OF_TRUST
 	select SHA_HW_ACCEL
 	select SHA_PROG_HW_ACCEL
 	select ENV_IS_NOWHERE
+	select SYS_CPC_REINIT_F if MPC85xx && !SYS_RAMBOOT
 	select CMD_EXT4 if ARM
 	select CMD_EXT4_WRITE if ARM
 	imply CMD_BLOB
@@ -75,6 +76,46 @@ config SPL_UBOOT_KEY_HASH
 	  41066b564c6ffcef40ccbc1e0a5d0d519604000c785d97bbefd25e4d288d1c8b.
 	  Otherwise leave this empty.
 
+if PPC
+
+config BOOTSCRIPT_COPY_RAM
+	bool "Secure boot copies boot script to RAM"
+	help
+	  On systems that support chain of trust booting, a number of addresses
+	  are required to set variables that are used in the copying and then
+	  verification of different parts of the system.  If enabled, the subsequent
+	  options are for what location to use in each step.
+
+config BS_ADDR_DEVICE
+	hex "Address in RAM for bs_device"
+	depends on BOOTSCRIPT_COPY_RAM
+
+config BS_SIZE
+	hex "The size of bs_size which is the amount read from bs_device"
+	depends on BOOTSCRIPT_COPY_RAM
+
+config BS_ADDR_RAM
+	hex "Address in RAM for bs_ram"
+	depends on BOOTSCRIPT_COPY_RAM
+
+config BS_HDR_ADDR_DEVICE
+	hex "Address in RAM for bs_hdr_device"
+	depends on BOOTSCRIPT_COPY_RAM
+
+config BS_HDR_SIZE
+	hex "The size of bs_hdr_size which is the amount read from bs_hdr_device"
+	depends on BOOTSCRIPT_COPY_RAM
+
+config BS_HDR_ADDR_RAM
+	hex "Address in RAM for bs_hdr_ram"
+	depends on BOOTSCRIPT_COPY_RAM
+
+config BOOTSCRIPT_HDR_ADDR
+	hex "CONFIG_BOOTSCRIPT_HDR_ADDR"
+	default BS_ADDR_RAM if BOOTSCRIPT_COPY_RAM
+
+endif
+
 config SYS_FSL_SRK_LE
 	def_bool y
 	depends on ARM
@@ -94,6 +135,26 @@ config DEEP_SLEEP
 	  Indicates this SoC supports deep sleep feature. If deep sleep is
 	  supported, core will start to execute uboot when wakes up.
 
+config LAYERSCAPE_NS_ACCESS
+	bool "Layerscape non-secure access support"
+	depends on ARCH_LS1021A || FSL_LSCH2
+
+config PCIE1
+	bool "PCIe controller #1"
+	depends on LAYERSCAPE_NS_ACCESS || PPC
+
+config PCIE2
+	bool "PCIe controller #2"
+	depends on LAYERSCAPE_NS_ACCESS || PPC
+
+config PCIE3
+	bool "PCIe controller #3"
+	depends on LAYERSCAPE_NS_ACCESS || PPC
+
+config PCIE4
+	bool "PCIe controller #4"
+	depends on LAYERSCAPE_NS_ACCESS || PPC
+
 config FSL_USE_PCA9547_MUX
 	bool "Enable PCA9547 I2C Mux on Freescale boards"
 	depends on PPC || ARCH_LS1021A || FSL_LSCH2 || FSL_LSCH3
@@ -166,6 +227,18 @@ config VOL_MONITOR_ISL68233_SET
 
 endif
 
+config SYS_FSL_NUM_CC_PLLS
+	int "Number of clock control PLLs"
+	depends on MPC85xx || FSL_LSCH2 || FSL_LSCH3 || ARCH_LS1021A || ARCH_LS1028A
+	default 2 if ARCH_LS1021A || ARCH_LS1028A || FSL_LSCH2
+	default 6 if FSL_LSCH3 || MPC85xx
+
+config SYS_FSL_ESDHC_BE
+	bool
+
+config SYS_FSL_IFC_BE
+	bool
+
 config FSL_QIXIS
 	bool "Enable QIXIS support"
 	depends on PPC || ARCH_LS1021A || FSL_LSCH2 || FSL_LSCH3