X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=README;h=f79a7331b2191df3b42a5e84e8907c0fec45f13f;hb=4c97c8cd425ff71004cdd9892ca37d46897a7084;hp=d6ff909e9a44d6ca8fe97244f197af17f719f4ed;hpb=931bad1c72b5cdc030f4b972420f62de306e11d2;p=platform%2Fkernel%2Fu-boot.git

diff --git a/README b/README
index d6ff909..f79a733 100644
--- a/README
+++ b/README
@@ -2130,24 +2130,6 @@ Low Level (hardware related) configuration options:
 		U-Boot uses the following memory types:
 		- MPC8xx: IMMR (internal memory of the CPU)
 
-- CONFIG_SYS_GBL_DATA_OFFSET:
-
-		Offset of the initial data structure in the memory
-		area defined by CONFIG_SYS_INIT_RAM_ADDR. Usually
-		CONFIG_SYS_GBL_DATA_OFFSET is chosen such that the initial
-		data is located at the end of the available space
-		(sometimes written as (CONFIG_SYS_INIT_RAM_SIZE -
-		GENERATED_GBL_DATA_SIZE), and the initial stack is just
-		below that area (growing from (CONFIG_SYS_INIT_RAM_ADDR +
-		CONFIG_SYS_GBL_DATA_OFFSET) downward.
-
-	Note:
-		On the MPC824X (or other systems that use the data
-		cache for initial memory) the address chosen for
-		CONFIG_SYS_INIT_RAM_ADDR is basically arbitrary - it must
-		point to an otherwise UNUSED address space between
-		the top of RAM and the start of the PCI space.
-
 - CONFIG_SYS_SCCR:	System Clock and reset Control Register (15-27)
 
 - CONFIG_SYS_OR_TIMING_SDRAM: