X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=README;h=ec1b50c30551bd959fe2e374770973a55e37ccbe;hb=e45d22655aed0c81fa5890f47c1647c6e95bedb6;hp=f79a7331b2191df3b42a5e84e8907c0fec45f13f;hpb=4c97c8cd425ff71004cdd9892ca37d46897a7084;p=platform%2Fkernel%2Fu-boot.git diff --git a/README b/README index f79a733..ec1b50c 100644 --- a/README +++ b/README @@ -166,27 +166,6 @@ Directory Hierarchy: Software Configuration: ======================= -Configuration is usually done using C preprocessor defines; the -rationale behind that is to avoid dead code whenever possible. - -There are two classes of configuration variables: - -* Configuration _OPTIONS_: - These are selectable by the user and have names beginning with - "CONFIG_". - -* Configuration _SETTINGS_: - These depend on the hardware etc. and should not be meddled with if - you don't know what you're doing; they have names beginning with - "CONFIG_SYS_". - -Previously, all configuration was done by hand, which involved creating -symbolic links and editing configuration files manually. More recently, -U-Boot has added the Kbuild infrastructure used by the Linux kernel, -allowing you to use the "make menuconfig" command to configure your -build. - - Selection of Processor Architecture and Board Type: --------------------------------------------------- @@ -293,33 +272,6 @@ board_init_r(): SPL-specific notes: - stack is optionally in SDRAM, if CONFIG_SPL_STACK_R is defined and - CONFIG_SPL_STACK_R_ADDR points into SDRAM - - preloader_console_init() can be called here - typically this is - done by selecting CONFIG_SPL_BOARD_INIT and then supplying a - spl_board_init() function containing this call - - loads U-Boot or (in falcon mode) Linux - - -Configuration Options: ----------------------- - -Configuration depends on the combination of board and CPU type; all -such information is kept in a configuration file -"include/configs/.h". - -Example: For a TQM823L module, all configuration settings are in -"include/configs/TQM823L.h". - - -Many of the options are named exactly as the corresponding Linux -kernel configuration options. The intention is to make it easier to -build a config tool - later. - -- ARM Platform Bus Type(CCI): - CoreLink Cache Coherent Interconnect (CCI) is ARM BUS which - provides full cache coherency between two clusters of multi-core - CPUs and I/O coherency for devices and I/O masters - CONFIG_SYS_FSL_HAS_CCI400 Defined For SoC that has cache coherent interconnect @@ -342,17 +294,6 @@ The following options need to be configured: the "64" category of the Power ISA). This is necessary for ePAPR compliance, among other possible reasons. - CONFIG_SYS_FSL_TBCLK_DIV - - Defines the core time base clock divider ratio compared to the - system clock. On most PQ3 devices this is 8, on newer QorIQ - devices it can be 16 or 32. The ratio varies from SoC to Soc. - - CONFIG_SYS_FSL_PCIE_COMPAT - - Defines the string to utilize when trying to match PCIe device - tree nodes for the given platform. - CONFIG_SYS_FSL_ERRATUM_A004510 Enables a workaround for erratum A004510. If set, @@ -378,35 +319,12 @@ The following options need to be configured: This is the value to write into CCSR offset 0x18600 according to the A004510 workaround. - CONFIG_SYS_FSL_DSP_DDR_ADDR - This value denotes start offset of DDR memory which is - connected exclusively to the DSP cores. - - CONFIG_SYS_FSL_DSP_M2_RAM_ADDR - This value denotes start offset of M2 memory - which is directly connected to the DSP core. - - CONFIG_SYS_FSL_DSP_M3_RAM_ADDR - This value denotes start offset of M3 memory which is directly - connected to the DSP core. - - CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT - This value denotes start offset of DSP CCSR space. - CONFIG_SYS_FSL_SINGLE_SOURCE_CLK Single Source Clock is clocking mode present in some of FSL SoC's. In this mode, a single differential clock is used to supply clocks to the sysclock, ddrclock and usbclock. - CONFIG_SYS_CPC_REINIT_F - This CONFIG is defined when the CPC is configured as SRAM at the - time of U-Boot entry and is required to be re-initialized. - - Generic CPU options: - CONFIG_SYS_BIG_ENDIAN, CONFIG_SYS_LITTLE_ENDIAN - - Defines the endianess of the CPU. Implementation of those - values is arch specific. CONFIG_SYS_FSL_DDR Freescale DDR driver in use. This type of DDR controller is @@ -415,90 +333,18 @@ The following options need to be configured: CONFIG_SYS_FSL_DDR_ADDR Freescale DDR memory-mapped register base. - CONFIG_SYS_FSL_DDR_EMU - Specify emulator support for DDR. Some DDR features such as - deskew training are not available. - - CONFIG_SYS_FSL_DDRC_GEN1 - Freescale DDR1 controller. - - CONFIG_SYS_FSL_DDRC_GEN2 - Freescale DDR2 controller. - - CONFIG_SYS_FSL_DDRC_GEN3 - Freescale DDR3 controller. - - CONFIG_SYS_FSL_DDRC_GEN4 - Freescale DDR4 controller. - - CONFIG_SYS_FSL_DDRC_ARM_GEN3 - Freescale DDR3 controller for ARM-based SoCs. - - CONFIG_SYS_FSL_DDR1 - Board config to use DDR1. It can be enabled for SoCs with - Freescale DDR1 or DDR2 controllers, depending on the board - implemetation. - - CONFIG_SYS_FSL_DDR2 - Board config to use DDR2. It can be enabled for SoCs with - Freescale DDR2 or DDR3 controllers, depending on the board - implementation. - - CONFIG_SYS_FSL_DDR3 - Board config to use DDR3. It can be enabled for SoCs with - Freescale DDR3 or DDR3L controllers. - - CONFIG_SYS_FSL_DDR3L - Board config to use DDR3L. It can be enabled for SoCs with - DDR3L controllers. - - CONFIG_SYS_FSL_IFC_BE - Defines the IFC controller register space as Big Endian - - CONFIG_SYS_FSL_IFC_LE - Defines the IFC controller register space as Little Endian - CONFIG_SYS_FSL_IFC_CLK_DIV Defines divider of platform clock(clock input to IFC controller). CONFIG_SYS_FSL_LBC_CLK_DIV Defines divider of platform clock(clock input to eLBC controller). - CONFIG_SYS_FSL_DDR_BE - Defines the DDR controller register space as Big Endian - - CONFIG_SYS_FSL_DDR_LE - Defines the DDR controller register space as Little Endian - CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY Physical address from the view of DDR controllers. It is the same as CONFIG_SYS_DDR_SDRAM_BASE for all Power SoCs. But it could be different for ARM SoCs. - CONFIG_SYS_FSL_DDR_INTLV_256B - DDR controller interleaving on 256-byte. This is a special - interleaving mode, handled by Dickens for Freescale layerscape - SoCs with ARM core. - - CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS - Number of controllers used as main memory. - - CONFIG_SYS_FSL_OTHER_DDR_NUM_CTRLS - Number of controllers used for other than main memory. - - CONFIG_SYS_FSL_SEC_BE - Defines the SEC controller register space as Big Endian - - CONFIG_SYS_FSL_SEC_LE - Defines the SEC controller register space as Little Endian - - MIPS CPU options: - CONFIG_SYS_INIT_SP_OFFSET - - Offset relative to CONFIG_SYS_SDRAM_BASE for initial stack - pointer. This is needed for the temporary stack before - relocation. - CONFIG_XWAY_SWAP_BYTES Enable compilation of tools/xway-swap-bytes needed for Lantiq @@ -569,8 +415,6 @@ The following options need to be configured: the defaults discussed just above. - Cache Configuration for ARM: - CONFIG_SYS_L2_PL310 - Enable support for ARM PL310 L2 cache - controller CONFIG_SYS_PL310_BASE - Physical base address of PL310 controller register space @@ -697,18 +541,6 @@ The following options need to be configured: CONFIG_SCSI) you must configure support for at least one non-MTD partition type as well. -- LBA48 Support - CONFIG_LBA48 - - Set this to enable support for disks larger than 137GB - Also look at CONFIG_SYS_64BIT_LBA. - Whithout these , LBA48 support uses 32bit variables and will 'only' - support disks up to 2.1TB. - - CONFIG_SYS_64BIT_LBA: - When enabled, makes the IDE subsystem use 64bit sector addresses. - Default is 32bit. - - NETWORK Support (PCI): CONFIG_E1000_SPI Utility code for direct access to the SPI bus on Intel 8257x. @@ -731,20 +563,6 @@ The following options need to be configured: CONFIG_LAN91C96_USE_32_BIT Define this to enable 32 bit addressing - CONFIG_SMC91111 - Support for SMSC's LAN91C111 chip - - CONFIG_SMC91111_BASE - Define this to hold the physical address - of the device (I/O space) - - CONFIG_SMC_USE_32_BIT - Define this if data bus is 32 bits - - CONFIG_SMC_USE_IOFUNCS - Define this to use i/o functions instead of macros - (some hardware wont work with macros) - CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT Define this if you have more then 3 PHYs. @@ -826,9 +644,6 @@ The following options need to be configured: Supported are USB Keyboards and USB Floppy drives (TEAC FD-05PUB). - CONFIG_USB_EHCI_TXFIFO_THRESH enables setting of the - txfilltuning field in the EHCI controller on reset. - CONFIG_USB_DWC2_REG_ADDR the physical CPU address of the DWC2 HW module registers. @@ -902,13 +717,6 @@ The following options need to be configured: the appropriate value in Hz. - MMC Support: - The MMC controller on the Intel PXA is supported. To - enable this define CONFIG_MMC. The MMC can be - accessed from the boot prompt by mapping the device - to physical memory similar to flash. Command line is - enabled with CONFIG_CMD_MMC. The MMC driver also works with - the FAT fs. This is enabled with CONFIG_CMD_FAT. - CONFIG_SH_MMCIF Support for Renesas on-chip MMCIF controller @@ -962,80 +770,6 @@ The following options need to be configured: - Keyboard Support: See Kconfig help for available keyboard drivers. -- LCD Support: CONFIG_LCD - - Define this to enable LCD support (for output to LCD - display); also select one of the supported displays - by defining one of these: - - CONFIG_NEC_NL6448AC33: - - NEC NL6448AC33-18. Active, color, single scan. - - CONFIG_NEC_NL6448BC20 - - NEC NL6448BC20-08. 6.5", 640x480. - Active, color, single scan. - - CONFIG_NEC_NL6448BC33_54 - - NEC NL6448BC33-54. 10.4", 640x480. - Active, color, single scan. - - CONFIG_SHARP_16x9 - - Sharp 320x240. Active, color, single scan. - It isn't 16x9, and I am not sure what it is. - - CONFIG_SHARP_LQ64D341 - - Sharp LQ64D341 display, 640x480. - Active, color, single scan. - - CONFIG_HLD1045 - - HLD1045 display, 640x480. - Active, color, single scan. - - CONFIG_OPTREX_BW - - Optrex CBL50840-2 NF-FW 99 22 M5 - or - Hitachi LMG6912RPFC-00T - or - Hitachi SP14Q002 - - 320x240. Black & white. - - CONFIG_LCD_ALIGNMENT - - Normally the LCD is page-aligned (typically 4KB). If this is - defined then the LCD will be aligned to this value instead. - For ARM it is sometimes useful to use MMU_SECTION_SIZE - here, since it is cheaper to change data cache settings on - a per-section basis. - - - CONFIG_LCD_ROTATION - - Sometimes, for example if the display is mounted in portrait - mode or even if it's mounted landscape but rotated by 180degree, - we need to rotate our content of the display relative to the - framebuffer, so that user can read the messages which are - printed out. - Once CONFIG_LCD_ROTATION is defined, the lcd_console will be - initialized with a given rotation from "vl_rot" out of - "vidinfo_t" which is provided by the board specific code. - The value for vl_rot is coded as following (matching to - fbcon=rotate: linux-kernel commandline): - 0 = no rotation respectively 0 degree - 1 = 90 degree rotation - 2 = 180 degree rotation - 3 = 270 degree rotation - - If CONFIG_LCD_ROTATION is not defined, the console will be - initialized with 0degree rotation. - - MII/PHY support: CONFIG_PHY_CLOCK_FREQ (ppc4xx) @@ -1354,11 +1088,6 @@ The following options need to be configured: will skip addresses 0x50 and 0x68 on bus 0 and address 0x54 on bus 1 - CONFIG_SYS_SPD_BUS_NUM - - If defined, then this indicates the I2C bus number for DDR SPD. - If not defined, then U-Boot assumes that SPD is on I2C bus 0. - CONFIG_SYS_RTC_BUS_NUM If defined, then this indicates the I2C bus number for the RTC. @@ -1398,14 +1127,6 @@ The following options need to be configured: Enables support for FPGA family. (SPARTAN2, SPARTAN3, VIRTEX2, CYCLONE2, ACEX1K, ACEX) - CONFIG_FPGA_COUNT - - Specify the number of FPGA devices to support. - - CONFIG_SYS_FPGA_PROG_FEEDBACK - - Enable printing of hash marks during FPGA configuration. - CONFIG_SYS_FPGA_CHECK_BUSY Enable checks on FPGA configuration interface busy @@ -1418,9 +1139,6 @@ The following options need to be configured: If defined, a function that provides delays in the FPGA configuration driver. - CONFIG_SYS_FPGA_CHECK_CTRLC - Allow Control-C to interrupt FPGA configuration - CONFIG_SYS_FPGA_CHECK_ERROR Check for configuration errors during FPGA bitfile @@ -1570,20 +1288,6 @@ The following options need to be configured: overwriting the architecture dependent default settings. -- Frame Buffer Address: - CONFIG_FB_ADDR - - Define CONFIG_FB_ADDR if you want to use specific - address for frame buffer. This is typically the case - when using a graphics controller has separate video - memory. U-Boot will then place the frame buffer at - the given address instead of dynamically reserving it - in system RAM by calling lcd_setmem(), which grabs - the memory for the frame buffer depending on the - configured panel size. - - Please see board_init_f function. - - Automatic software updates via TFTP server CONFIG_UPDATE_TFTP CONFIG_UPDATE_TFTP_CNT_MAX @@ -1658,16 +1362,6 @@ The following options need to be configured: CONFIG_SPL Enable building of SPL globally. - CONFIG_SPL_RELOC_TEXT_BASE - Address to relocate to. If unspecified, this is equal to - CONFIG_SPL_TEXT_BASE (i.e. no relocation is done). - - CONFIG_SPL_BSS_START_ADDR - Link address for the BSS within the SPL binary. - - CONFIG_SPL_STACK - Adress of the start of the stack SPL will use - CONFIG_SPL_PANIC_ON_RAW_IMAGE When defined, SPL will panic() if the image it has loaded does not have a signature. @@ -1678,30 +1372,10 @@ The following options need to be configured: consider that a completely unreadable NAND block is bad, and thus should be skipped silently. - CONFIG_SPL_RELOC_STACK - Adress of the start of the stack SPL will use after - relocation. If unspecified, this is equal to - CONFIG_SPL_STACK. - - CONFIG_SYS_SPL_MALLOC_START - Starting address of the malloc pool used in SPL. - When this option is set the full malloc is used in SPL and - it is set up by spl_init() and before that, the simple malloc() - can be used if CONFIG_SYS_MALLOC_F is defined. - - CONFIG_SYS_SPL_MALLOC_SIZE - The size of the malloc pool used in SPL. - CONFIG_SPL_DISPLAY_PRINT For ARM, enable an optional function to print more information about the running system. - CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR, - CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS - Sector and number of sectors to load kernel argument - parameters from when MMC is being used in raw mode - (for falcon mode) - CONFIG_SPL_MPC83XX_WAIT_FOR_NAND Set this for NAND SPL on PPC mpc83xx targets, so that start.S waits for the rest of the SPL to load before @@ -1736,11 +1410,6 @@ The following options need to be configured: CONFIG_SPL_RAM_DEVICE Support for running image already present in ram, in SPL binary - CONFIG_SPL_TARGET - Final target image containing SPL and payload. Some SPLs - use an arch-specific makefile fragment instead, for - example if more than one image needs to be produced. - CONFIG_SPL_FIT_PRINT Printing information about a FIT image adds quite a bit of code to SPL. So this is normally disabled in SPL. Use this @@ -1836,7 +1505,7 @@ Configuration Settings: - CONFIG_SYS_MALLOC_SIMPLE Provides a simple and small malloc() and calloc() for those boards which do not use the full malloc in SPL (which is - enabled with CONFIG_SYS_SPL_MALLOC_START). + enabled with CONFIG_SYS_SPL_MALLOC). - CONFIG_SYS_NONCACHED_MEMORY: Size of non-cached memory area. This area of memory will be @@ -1857,12 +1526,6 @@ Configuration Settings: Non-cached memory is only supported on 32-bit ARM at present. -- CONFIG_SYS_BOOTM_LEN: - Normally compressed uImages are limited to an - uncompressed size of 8 MBytes. If this is not enough, - you can define CONFIG_SYS_BOOTM_LEN in your board config file - to adjust this setting to your needs. - - CONFIG_SYS_BOOTMAPSZ: Maximum size of memory mapped by the startup code of the Linux kernel; all data that must be processed by @@ -1875,11 +1538,6 @@ Configuration Settings: CONFIG_SYS_BOOTMAPSZ. If CONFIG_SYS_BOOTMAPSZ is undefined, then the value in "bootm_size" will be used instead. -- CONFIG_SYS_BOOT_RAMDISK_HIGH: - Enable initrd_high functionality. If defined then the - initrd_high feature is enabled and the bootm ramdisk subcommand - is enabled. - - CONFIG_SYS_BOOT_GET_CMDLINE: Enables allocating and saving kernel cmdline in space between "bootm_low" and "bootm_low" + BOOTMAPSZ. @@ -1888,38 +1546,10 @@ Configuration Settings: Enables allocating and saving a kernel copy of the bd_info in space between "bootm_low" and "bootm_low" + BOOTMAPSZ. -- CONFIG_SYS_MAX_FLASH_SECT: - Max number of sectors on a Flash chip - -- CONFIG_SYS_FLASH_ERASE_TOUT: - Timeout for Flash erase operations (in ms) - -- CONFIG_SYS_FLASH_WRITE_TOUT: - Timeout for Flash write operations (in ms) - -- CONFIG_SYS_FLASH_LOCK_TOUT - Timeout for Flash set sector lock bit operation (in ms) - -- CONFIG_SYS_FLASH_UNLOCK_TOUT - Timeout for Flash clear lock bits operation (in ms) - - CONFIG_SYS_FLASH_PROTECTION If defined, hardware flash sectors protection is used instead of U-Boot software protection. -- CONFIG_SYS_DIRECT_FLASH_TFTP: - - Enable TFTP transfers directly to flash memory; - without this option such a download has to be - performed in two steps: (1) download to RAM, and (2) - copy from RAM to flash. - - The two-step approach is usually more reliable, since - you can check if the download worked before you erase - the flash, but in some situations (when system RAM is - too limited to allow for a temporary copy of the - downloaded image) this option may be very useful. - - CONFIG_SYS_FLASH_CFI: Define if the flash driver uses extra elements in the common flash structure for storing flash geometry. @@ -1940,12 +1570,6 @@ Configuration Settings: s29ws-n MirrorBit flash has non-standard addresses for buffered write commands. -- CONFIG_SYS_FLASH_QUIET_TEST - If this option is defined, the common CFI flash doesn't - print it's warning upon not recognized FLASH banks. This - is useful, if some of the configured banks are only - optionally available. - - CONFIG_FLASH_SHOW_PROGRESS If defined (must be an integer), print out countdown digits and dots. Recommended value: 45 (9..1) for 80 @@ -1960,14 +1584,6 @@ Configuration Settings: while unprotecting/erasing/programming. Please only enable this option if you really know what you are doing. -- CONFIG_ENV_MAX_ENTRIES - - Maximum number of entries in the hash table that is used - internally to store the environment settings. The default - setting is supposed to be generous and should work in most - cases. This setting can be used to tune behaviour; see - lib/hashtable.c for details. - - CONFIG_ENV_FLAGS_LIST_DEFAULT - CONFIG_ENV_FLAGS_LIST_STATIC Enable validation of the values given to environment variables when @@ -2183,12 +1799,6 @@ Low Level (hardware related) configuration options: one, specify here. Note that the value must resolve to something your driver can deal with. -- CONFIG_SYS_DDR_RAW_TIMING - Get DDR timing information from other than SPD. Common with - soldered DDR chips onboard without SPD. DDR raw timing - parameters are extracted from datasheet and hard-coded into - header files or board specific files. - - CONFIG_FSL_DDR_INTERACTIVE Enable interactive DDR debugging. See doc/README.fsl-ddr. @@ -2198,10 +1808,6 @@ Low Level (hardware related) configuration options: - CONFIG_FSL_DDR_BIST Enable built-in memory test for Freescale DDR controllers. -- CONFIG_SYS_83XX_DDR_USES_CS0 - Only for 83xx systems. If specified, then DDR should - be configured using CS0 and CS1 instead of CS2 and CS3. - - CONFIG_RMII Enable RMII mode for all FECs. Note that this is a global option, we can't @@ -2247,11 +1853,6 @@ Low Level (hardware related) configuration options: proper). Code that needs stage-specific behavior should check this. -- CONFIG_SYS_MPC85XX_NO_RESETVEC - Only for 85xx systems. If this variable is specified, the section - .resetvec is not kept and the section .bootpg is placed in the - previous 4k of the .text section. - - CONFIG_ARCH_MAP_SYSMEM Generally U-Boot (and in particular the md command) uses effective address. It is therefore not necessary to regard @@ -2483,6 +2084,7 @@ rarpboot- boot image via network using RARP/TFTP protocol diskboot- boot from IDE devicebootd - boot default, i.e., run 'bootcmd' loads - load S-Record file over serial line loadb - load binary file over serial line (kermit mode) +loadm - load binary blob from source address to destination address md - memory display mm - memory modify (auto-incrementing) nm - memory modify (constant address)