X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=README;h=e01ff989bd4b1981efb9515f268d95c6d08e425a;hb=0a816d92d581749341c0c725816efe930e56e2a4;hp=f79a7331b2191df3b42a5e84e8907c0fec45f13f;hpb=4c97c8cd425ff71004cdd9892ca37d46897a7084;p=platform%2Fkernel%2Fu-boot.git diff --git a/README b/README index f79a733..e01ff98 100644 --- a/README +++ b/README @@ -293,33 +293,6 @@ board_init_r(): SPL-specific notes: - stack is optionally in SDRAM, if CONFIG_SPL_STACK_R is defined and - CONFIG_SPL_STACK_R_ADDR points into SDRAM - - preloader_console_init() can be called here - typically this is - done by selecting CONFIG_SPL_BOARD_INIT and then supplying a - spl_board_init() function containing this call - - loads U-Boot or (in falcon mode) Linux - - -Configuration Options: ----------------------- - -Configuration depends on the combination of board and CPU type; all -such information is kept in a configuration file -"include/configs/.h". - -Example: For a TQM823L module, all configuration settings are in -"include/configs/TQM823L.h". - - -Many of the options are named exactly as the corresponding Linux -kernel configuration options. The intention is to make it easier to -build a config tool - later. - -- ARM Platform Bus Type(CCI): - CoreLink Cache Coherent Interconnect (CCI) is ARM BUS which - provides full cache coherency between two clusters of multi-core - CPUs and I/O coherency for devices and I/O masters - CONFIG_SYS_FSL_HAS_CCI400 Defined For SoC that has cache coherent interconnect @@ -493,12 +466,6 @@ The following options need to be configured: Defines the SEC controller register space as Little Endian - MIPS CPU options: - CONFIG_SYS_INIT_SP_OFFSET - - Offset relative to CONFIG_SYS_SDRAM_BASE for initial stack - pointer. This is needed for the temporary stack before - relocation. - CONFIG_XWAY_SWAP_BYTES Enable compilation of tools/xway-swap-bytes needed for Lantiq @@ -826,9 +793,6 @@ The following options need to be configured: Supported are USB Keyboards and USB Floppy drives (TEAC FD-05PUB). - CONFIG_USB_EHCI_TXFIFO_THRESH enables setting of the - txfilltuning field in the EHCI controller on reset. - CONFIG_USB_DWC2_REG_ADDR the physical CPU address of the DWC2 HW module registers. @@ -1658,16 +1622,6 @@ The following options need to be configured: CONFIG_SPL Enable building of SPL globally. - CONFIG_SPL_RELOC_TEXT_BASE - Address to relocate to. If unspecified, this is equal to - CONFIG_SPL_TEXT_BASE (i.e. no relocation is done). - - CONFIG_SPL_BSS_START_ADDR - Link address for the BSS within the SPL binary. - - CONFIG_SPL_STACK - Adress of the start of the stack SPL will use - CONFIG_SPL_PANIC_ON_RAW_IMAGE When defined, SPL will panic() if the image it has loaded does not have a signature. @@ -1678,30 +1632,10 @@ The following options need to be configured: consider that a completely unreadable NAND block is bad, and thus should be skipped silently. - CONFIG_SPL_RELOC_STACK - Adress of the start of the stack SPL will use after - relocation. If unspecified, this is equal to - CONFIG_SPL_STACK. - - CONFIG_SYS_SPL_MALLOC_START - Starting address of the malloc pool used in SPL. - When this option is set the full malloc is used in SPL and - it is set up by spl_init() and before that, the simple malloc() - can be used if CONFIG_SYS_MALLOC_F is defined. - - CONFIG_SYS_SPL_MALLOC_SIZE - The size of the malloc pool used in SPL. - CONFIG_SPL_DISPLAY_PRINT For ARM, enable an optional function to print more information about the running system. - CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR, - CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS - Sector and number of sectors to load kernel argument - parameters from when MMC is being used in raw mode - (for falcon mode) - CONFIG_SPL_MPC83XX_WAIT_FOR_NAND Set this for NAND SPL on PPC mpc83xx targets, so that start.S waits for the rest of the SPL to load before @@ -1736,11 +1670,6 @@ The following options need to be configured: CONFIG_SPL_RAM_DEVICE Support for running image already present in ram, in SPL binary - CONFIG_SPL_TARGET - Final target image containing SPL and payload. Some SPLs - use an arch-specific makefile fragment instead, for - example if more than one image needs to be produced. - CONFIG_SPL_FIT_PRINT Printing information about a FIT image adds quite a bit of code to SPL. So this is normally disabled in SPL. Use this @@ -1836,7 +1765,7 @@ Configuration Settings: - CONFIG_SYS_MALLOC_SIMPLE Provides a simple and small malloc() and calloc() for those boards which do not use the full malloc in SPL (which is - enabled with CONFIG_SYS_SPL_MALLOC_START). + enabled with CONFIG_SYS_SPL_MALLOC). - CONFIG_SYS_NONCACHED_MEMORY: Size of non-cached memory area. This area of memory will be @@ -2483,6 +2412,7 @@ rarpboot- boot image via network using RARP/TFTP protocol diskboot- boot from IDE devicebootd - boot default, i.e., run 'bootcmd' loads - load S-Record file over serial line loadb - load binary file over serial line (kermit mode) +loadm - load binary blob from source address to destination address md - memory display mm - memory modify (auto-incrementing) nm - memory modify (constant address)