X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=README;h=d75c3fbc8596c94591bcf3aecd70e439bd8684ea;hb=4d89330b8ac1852e14f079ead75021a17b4b744e;hp=186f1f9a5ffb8161c51cfdf4e72daaf5d0e8c97b;hpb=e9a1ff9724348408144c7f1c5b5cc26130ba46e5;p=platform%2Fkernel%2Fu-boot.git diff --git a/README b/README index 186f1f9..d75c3fb 100644 --- a/README +++ b/README @@ -298,7 +298,7 @@ The following options need to be configured: Enables a workaround for erratum A004510. If set, then CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV and - CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY must be set. + CFG_SYS_FSL_CORENET_SNOOPVEC_COREONLY must be set. CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 (optional) @@ -314,7 +314,7 @@ The following options need to be configured: See Freescale App Note 4493 for more information about this erratum. - CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY + CFG_SYS_FSL_CORENET_SNOOPVEC_COREONLY This is the value to write into CCSR offset 0x18600 according to the A004510 workaround. @@ -330,7 +330,7 @@ The following options need to be configured: Freescale DDR driver in use. This type of DDR controller is found in mpc83xx, mpc85xx as well as some ARM core SoCs. - CONFIG_SYS_FSL_DDR_ADDR + CFG_SYS_FSL_DDR_ADDR Freescale DDR memory-mapped register base. CONFIG_SYS_FSL_IFC_CLK_DIV @@ -339,7 +339,7 @@ The following options need to be configured: CONFIG_SYS_FSL_LBC_CLK_DIV Defines divider of platform clock(clock input to eLBC controller). - CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY + CFG_SYS_FSL_DDR_SDRAM_BASE_PHY Physical address from the view of DDR controllers. It is the same as CONFIG_SYS_DDR_SDRAM_BASE for all Power SoCs. But it could be different for ARM SoCs. @@ -435,15 +435,6 @@ The following options need to be configured: Define this variable to enable hw flow control in serial driver. Current user of this option is drivers/serial/nsl16550.c driver -- Serial Download Echo Mode: - CONFIG_LOADS_ECHO - If defined to 1, all characters received during a - serial download (using the "loads" command) are - echoed back. This might be needed by some terminal - emulations (like "cu"), but may as well just take - time on others. This setting #define's the initial - value of the "loads_echo" environment variable. - - Removal of commands If no commands are needed to boot, you can disable CONFIG_CMDLINE to remove them. In this case, the command line @@ -762,88 +753,9 @@ The following options need to be configured: entering dfuMANIFEST state. Host waits this timeout, before sending again an USB request to the device. -- Journaling Flash filesystem support: - CONFIG_SYS_JFFS2_FIRST_SECTOR, - CONFIG_SYS_JFFS2_FIRST_BANK, CONFIG_SYS_JFFS2_NUM_BANKS - Define these for a default partition on a NOR device - - Keyboard Support: See Kconfig help for available keyboard drivers. -- LCD Support: CONFIG_LCD - - Define this to enable LCD support (for output to LCD - display); also select one of the supported displays - by defining one of these: - - CONFIG_NEC_NL6448AC33: - - NEC NL6448AC33-18. Active, color, single scan. - - CONFIG_NEC_NL6448BC20 - - NEC NL6448BC20-08. 6.5", 640x480. - Active, color, single scan. - - CONFIG_NEC_NL6448BC33_54 - - NEC NL6448BC33-54. 10.4", 640x480. - Active, color, single scan. - - CONFIG_SHARP_16x9 - - Sharp 320x240. Active, color, single scan. - It isn't 16x9, and I am not sure what it is. - - CONFIG_SHARP_LQ64D341 - - Sharp LQ64D341 display, 640x480. - Active, color, single scan. - - CONFIG_HLD1045 - - HLD1045 display, 640x480. - Active, color, single scan. - - CONFIG_OPTREX_BW - - Optrex CBL50840-2 NF-FW 99 22 M5 - or - Hitachi LMG6912RPFC-00T - or - Hitachi SP14Q002 - - 320x240. Black & white. - - CONFIG_LCD_ALIGNMENT - - Normally the LCD is page-aligned (typically 4KB). If this is - defined then the LCD will be aligned to this value instead. - For ARM it is sometimes useful to use MMU_SECTION_SIZE - here, since it is cheaper to change data cache settings on - a per-section basis. - - - CONFIG_LCD_ROTATION - - Sometimes, for example if the display is mounted in portrait - mode or even if it's mounted landscape but rotated by 180degree, - we need to rotate our content of the display relative to the - framebuffer, so that user can read the messages which are - printed out. - Once CONFIG_LCD_ROTATION is defined, the lcd_console will be - initialized with a given rotation from "vl_rot" out of - "vidinfo_t" which is provided by the board specific code. - The value for vl_rot is coded as following (matching to - fbcon=rotate: linux-kernel commandline): - 0 = no rotation respectively 0 degree - 1 = 90 degree rotation - 2 = 180 degree rotation - 3 = 270 degree rotation - - If CONFIG_LCD_ROTATION is not defined, the console will be - initialized with 0degree rotation. - - MII/PHY support: CONFIG_PHY_CLOCK_FREQ (ppc4xx) @@ -1126,17 +1038,6 @@ The following options need to be configured: You should define these to the GPIO value as given directly to the generic GPIO functions. - CONFIG_SYS_I2C_INIT_BOARD - - When a board is reset during an i2c bus transfer - chips might think that the current transfer is still - in progress. On some boards it is possible to access - the i2c SCLK line directly, either by using the - processor pin as a GPIO or by having a second pin - connected to the bus. If this option is defined a - custom i2c_init_board() routine in boards/xxx/board.c - is run early in the boot sequence. - CONFIG_I2C_MULTI_BUS This option allows the use of multiple I2C buses, each of which @@ -1545,21 +1446,12 @@ Configuration Settings: the RAM base is not zero, or RAM is divided into banks, this variable needs to be recalcuated to get the address. -- CONFIG_SYS_LOADS_BAUD_CHANGE: - Enable temporary baudrate change while serial download - - CONFIG_SYS_SDRAM_BASE: Physical start address of SDRAM. _Must_ be 0 here. - CONFIG_SYS_FLASH_BASE: Physical start address of Flash memory. -- CONFIG_SYS_MONITOR_LEN: - Size of memory reserved for monitor code, used to - determine _at_compile_time_ (!) if the environment is - embedded within the U-Boot image, or in a separate - flash sector. - - CONFIG_SYS_MALLOC_LEN: Size of DRAM reserved for malloc() use. @@ -1581,25 +1473,6 @@ Configuration Settings: boards which do not use the full malloc in SPL (which is enabled with CONFIG_SYS_SPL_MALLOC). -- CONFIG_SYS_NONCACHED_MEMORY: - Size of non-cached memory area. This area of memory will be - typically located right below the malloc() area and mapped - uncached in the MMU. This is useful for drivers that would - otherwise require a lot of explicit cache maintenance. For - some drivers it's also impossible to properly maintain the - cache. For example if the regions that need to be flushed - are not a multiple of the cache-line size, *and* padding - cannot be allocated between the regions to align them (i.e. - if the HW requires a contiguous array of regions, and the - size of each region is not cache-aligned), then a flush of - one region may result in overwriting data that hardware has - written to another region in the same cache-line. This can - happen for example in network drivers where descriptors for - buffers are typically smaller than the CPU cache-line (e.g. - 16 bytes vs. 32 or 64 bytes). - - Non-cached memory is only supported on 32-bit ARM at present. - - CONFIG_SYS_BOOTMAPSZ: Maximum size of memory mapped by the startup code of the Linux kernel; all data that must be processed by @@ -1825,9 +1698,6 @@ Low Level (hardware related) configuration options: - CONFIG_SYS_OR_TIMING_SDRAM: SDRAM timing -- CONFIG_SYS_MAMR_PTA: - periodic timer for refresh - - CONFIG_SYS_SRIO: Chip has SRIO or not