X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=README;h=176de61a331c36582cd6f1c2791e36c5e74ec382;hb=b2a6dfe4f8d263b9aa45929f1a40cd1143775a81;hp=a0646c36657b3b69b37a9a1816a27fcdb55d8d43;hpb=bf46e7d8d134521301ff02b6d97e8998aa10a83d;p=platform%2Fkernel%2Fu-boot.git

diff --git a/README b/README
index a0646c3..176de61 100644
--- a/README
+++ b/README
@@ -472,6 +472,15 @@ The following options need to be configured:
 		Board config to use DDR3. It can be enabled for SoCs with
 		Freescale DDR3 controllers.
 
+		CONFIG_SYS_FSL_PBL_PBI
+		It enables addition of RCW (Power on reset configuration) in built image.
+		Please refer doc/README.pblimage for more details
+
+		CONFIG_SYS_FSL_PBL_RCW
+		It adds PBI(pre-boot instructions) commands in u-boot build image.
+		PBI commands can be used to configure SoC before it starts the execution.
+		Please refer doc/README.pblimage for more details
+
 - Intel Monahans options:
 		CONFIG_SYS_MONAHANS_RUN_MODE_OSC_RATIO
 
@@ -2756,6 +2765,12 @@ CBFS (Coreboot Filesystem) support
 		Define this option to use the Bank addr/Extended addr
 		support on SPI flashes which has size > 16Mbytes.
 
+		CONFIG_SF_DUAL_FLASH		Dual flash memories
+
+		Define this option to use dual flash support where two flash
+		memories can be connected with a given cs line.
+		currently Xilinx Zynq qspi support these type of connections.
+
 - SystemACE Support:
 		CONFIG_SYSTEMACE