X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;ds=sidebyside;f=include%2Fconfigs%2Ftegra-common.h;h=717cd61bd69a9ba349b308fd9296272d22c37024;hb=HEAD;hp=2b968917d34d17d724d8cd4577f55d709bfa1f7c;hpb=3b191c56c841596771b4120f09fb556adf958b5c;p=platform%2Fkernel%2Fu-boot.git

diff --git a/include/configs/tegra-common.h b/include/configs/tegra-common.h
index 2b96891..c558679 100644
--- a/include/configs/tegra-common.h
+++ b/include/configs/tegra-common.h
@@ -12,42 +12,21 @@
 /*
  * High Level Configuration Options
  */
-#define CONFIG_SYS_L2CACHE_OFF		/* No L2 cache */
 
 #include <asm/arch/tegra.h>		/* get chip and board defs */
 
-/* Use the Tegra US timer on ARMv7, but the architected timer on ARMv8. */
-#ifndef CONFIG_ARM64
-#define CONFIG_SYS_TIMER_RATE		1000000
-#define CONFIG_SYS_TIMER_COUNTER	NV_PA_TMRUS_BASE
-#endif
-
-#define CONFIG_CMDLINE_TAG		/* enable passing of ATAGs */
-
 /* Environment */
 
 /*
  * NS16550 Configuration
  */
-#define CONFIG_SYS_NS16550_CLK		V_NS16550_CLK
-
-/*
- * Common HW configuration.
- * If this varies between SoCs later, move to tegraNN-common.h
- * Note: This is number of devices, not max device ID.
- */
-#define CONFIG_SYS_MMC_MAX_DEVICE 4
+#define CFG_SYS_NS16550_CLK		V_NS16550_CLK
 
-/*
- * Increasing the size of the IO buffer as default nfsargs size is more
- *  than 256 and so it is not possible to edit it
- */
-#define CONFIG_SYS_CBSIZE		(1024 * 2) /* Console I/O Buffer Size */
-/* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS		64	/* max number of command args */
-
-/* Boot Argument Buffer Size */
-#define CONFIG_SYS_BARGSIZE		(CONFIG_SYS_CBSIZE)
+#ifdef CONFIG_ARM64
+#define FDTFILE "nvidia/" CONFIG_DEFAULT_DEVICE_TREE ".dtb"
+#else
+#define FDTFILE CONFIG_DEFAULT_DEVICE_TREE ".dtb"
+#endif
 
 /*-----------------------------------------------------------------------
  * Physical Memory Map
@@ -55,23 +34,15 @@
 #define PHYS_SDRAM_1		NV_PA_SDRC_CS0
 #define PHYS_SDRAM_1_SIZE	0x20000000	/* 512M */
 
-#define CONFIG_SYS_SDRAM_BASE	PHYS_SDRAM_1
+#define CFG_SYS_SDRAM_BASE	PHYS_SDRAM_1
 
-#define CONFIG_SYS_BOOTMAPSZ	(256 << 20)	/* 256M */
+#define CFG_SYS_BOOTMAPSZ	(256 << 20)	/* 256M */
 
 #ifndef CONFIG_ARM64
-#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_STACKBASE
-#define CONFIG_SYS_INIT_RAM_SIZE	CONFIG_SYS_MALLOC_LEN
-#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR + \
-						CONFIG_SYS_INIT_RAM_SIZE - \
-						GENERATED_GBL_DATA_SIZE)
-#endif
+#define CFG_SYS_INIT_RAM_ADDR	CFG_STACKBASE
+#define CFG_SYS_INIT_RAM_SIZE	CONFIG_SYS_MALLOC_LEN
 
-#ifndef CONFIG_ARM64
 /* Defines for SPL */
-#define CONFIG_SPL_MAX_FOOTPRINT	(CONFIG_SYS_TEXT_BASE - \
-						CONFIG_SPL_TEXT_BASE)
-#define CONFIG_SYS_SPL_MALLOC_SIZE	0x00010000
 #endif
 
 #endif /* _TEGRA_COMMON_H_ */