X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;ds=sidebyside;f=include%2Fconfigs%2Fpm9g45.h;h=686411eee2eabe2a354d4cc0d21cdf1c85d0cd9b;hb=4db386655a889b6466d2c3f40839ad21205c6d21;hp=7d3a326deaf09873f5860de645a81033ee7b8b88;hpb=715cce65b889214a728dd44759204316aff29006;p=platform%2Fkernel%2Fu-boot.git

diff --git a/include/configs/pm9g45.h b/include/configs/pm9g45.h
index 7d3a326..686411e 100644
--- a/include/configs/pm9g45.h
+++ b/include/configs/pm9g45.h
@@ -16,22 +16,22 @@
 #define __CONFIG_H
 
 /* ARM asynchronous clock */
-#define CONFIG_SYS_AT91_SLOW_CLOCK      32768
-#define CONFIG_SYS_AT91_MAIN_CLOCK      12000000 /* from 12 MHz crystal */
+#define CFG_SYS_AT91_SLOW_CLOCK      32768
+#define CFG_SYS_AT91_MAIN_CLOCK      12000000 /* from 12 MHz crystal */
 
 /* SDRAM */
-#define CONFIG_SYS_SDRAM_BASE           0x70000000
-#define CONFIG_SYS_SDRAM_SIZE		0x08000000
+#define CFG_SYS_SDRAM_BASE           0x70000000
+#define CFG_SYS_SDRAM_SIZE		0x08000000
 
 /* NAND flash */
 #ifdef CONFIG_CMD_NAND
-#define CONFIG_SYS_NAND_BASE			ATMEL_BASE_CS3
+#define CFG_SYS_NAND_BASE			ATMEL_BASE_CS3
 /* our ALE is AD21 */
-#define CONFIG_SYS_NAND_MASK_ALE		BIT(21)
+#define CFG_SYS_NAND_MASK_ALE		BIT(21)
 /* our CLE is AD22 */
-#define CONFIG_SYS_NAND_MASK_CLE		BIT(22)
-#define CONFIG_SYS_NAND_ENABLE_PIN		AT91_PIN_PC14
-#define CONFIG_SYS_NAND_READY_PIN		AT91_PIN_PD3
+#define CFG_SYS_NAND_MASK_CLE		BIT(22)
+#define CFG_SYS_NAND_ENABLE_PIN		AT91_PIN_PC14
+#define CFG_SYS_NAND_READY_PIN		AT91_PIN_PD3
 #endif
 
 #ifdef CONFIG_NAND_BOOT
@@ -44,18 +44,18 @@
 
 #ifdef CONFIG_SD_BOOT
 #elif CONFIG_NAND_BOOT
-#define CONFIG_SYS_NAND_U_BOOT_SIZE	0x80000
+#define CFG_SYS_NAND_U_BOOT_SIZE	0x80000
 
-#define CONFIG_SYS_NAND_ECCSIZE		256
-#define CONFIG_SYS_NAND_ECCBYTES	3
-#define CONFIG_SYS_NAND_ECCPOS		{ 40, 41, 42, 43, 44, 45, 46, 47, \
+#define CFG_SYS_NAND_ECCSIZE		256
+#define CFG_SYS_NAND_ECCBYTES	3
+#define CFG_SYS_NAND_ECCPOS		{ 40, 41, 42, 43, 44, 45, 46, 47, \
 					  48, 49, 50, 51, 52, 53, 54, 55, \
 					  56, 57, 58, 59, 60, 61, 62, 63, }
 #endif
 
-#define CONFIG_SYS_MASTER_CLOCK		132096000
-#define CONFIG_SYS_AT91_PLLA		0x20c73f03
-#define CONFIG_SYS_MCKR			0x1301
-#define CONFIG_SYS_MCKR_CSS		0x1302
+#define CFG_SYS_MASTER_CLOCK		132096000
+#define CFG_SYS_AT91_PLLA		0x20c73f03
+#define CFG_SYS_MCKR			0x1301
+#define CFG_SYS_MCKR_CSS		0x1302
 
 #endif