X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;ds=sidebyside;f=include%2Fconfigs%2Fcsb472.h;h=d3e5ea86b1b5d2e7b41548e8ee850e10057bfacc;hb=d3c23a790fb24f9cb5cc467b81b0c3ad3eeb1f96;hp=316b1fee21d44fd0fdc72f37635d39d5dbae8e36;hpb=dcc0264878406d52b879d2e5a63d3d793371434e;p=platform%2Fkernel%2Fu-boot.git

diff --git a/include/configs/csb472.h b/include/configs/csb472.h
index 316b1fe..d3e5ea8 100644
--- a/include/configs/csb472.h
+++ b/include/configs/csb472.h
@@ -33,7 +33,7 @@
  * (easy to change)
  */
 
-#define CONFIG_405GP		1	/* This is a PPC405GP CPU     	*/
+#define CONFIG_405GP		1	/* This is a PPC405GP CPU	*/
 #define CONFIG_4xx		1	/* ...member of PPC4xx family   */
 #define CONFIG_CSB472		1	/* on a Cogent CSB472 board     */
 #define CONFIG_BOARD_EARLY_INIT_F 1	/* Call board_early_init_f()    */
@@ -73,12 +73,15 @@
 #endif
 
 /*
- * BOOTP/DHCP protocol configuration
- *
+ * BOOTP options
  */
-#define CONFIG_BOOTP_MASK	( CONFIG_BOOTP_DEFAULT		| \
-				  CONFIG_BOOTP_DNS2		| \
-				  CONFIG_BOOTP_BOOTFILESIZE	)
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_DNS2
+
 
 /*
  * Command line configuration.
@@ -178,7 +181,7 @@
  */
 #define CONFIG_MII		1	/* MII PHY management		*/
 #define CONFIG_PHY_ADDR		0	/* PHY address			*/
-#define CONFIG_PHY_CMD_DELAY	40	/* PHY COMMAND delay 		*/
+#define CONFIG_PHY_CMD_DELAY	40	/* PHY COMMAND delay		*/
 					/* 32usec min. for LXT971A	*/
 #define CONFIG_PHY_RESET_DELAY	300	/* PHY RESET recovery delay	*/
 
@@ -260,7 +263,7 @@
  *
  */
 #define CFG_FLASH_CFI		1	/* flash is CFI conformant	*/
-#define CFG_FLASH_CFI_DRIVER	1	/* use common cfi driver	*/
+#define CONFIG_FLASH_CFI_DRIVER	1	/* use common cfi driver	*/
 #define CFG_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster) */
 #define CFG_MAX_FLASH_BANKS	1	/* max # of memory banks	*/
 #define CFG_FLASH_INCREMENT	0	/* there is only one bank	*/
@@ -286,14 +289,6 @@
 #define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
 
 /*
- * Cache configuration
- *
- */
-#define CFG_DCACHE_SIZE		16384	/* For AMCC 405 CPUs, older 405 ppc's */
-					/* have only 8kB, 16kB is save here  */
-#define CFG_CACHELINE_SIZE	32
-
-/*
  * Miscellaneous board specific definitions
  *
  */