X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;ds=sidebyside;f=include%2Fconfigs%2FMPC8548CDS.h;h=190c668303a662533df6d625bd8cf914c1e01e6c;hb=1320112c8aa58345d71a5a46f3bf6a52589f1f2b;hp=ab887c1b9c37dfff125e20646e10c88714fa31c1;hpb=867b06f434a3184deeabd2bddb5178439dc6e445;p=platform%2Fkernel%2Fu-boot.git diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index ab887c1..190c668 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -1,23 +1,7 @@ /* * Copyright 2004, 2007, 2010-2011 Freescale Semiconductor. * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * SPDX-License-Identifier: GPL-2.0+ */ /* @@ -29,10 +13,13 @@ #ifndef __CONFIG_H #define __CONFIG_H +#ifdef CONFIG_36BIT +#define CONFIG_PHYS_64BIT +#endif + /* High Level Configuration Options */ #define CONFIG_BOOKE 1 /* BOOKE */ #define CONFIG_E500 1 /* BOOKE e500 family */ -#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */ #define CONFIG_MPC8548 1 /* MPC8548 specific */ #define CONFIG_MPC8548CDS 1 /* MPC8548CDS board specific */ @@ -48,6 +35,7 @@ #define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */ #undef CONFIG_PCI2 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ +#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ @@ -74,6 +62,11 @@ extern unsigned long get_clock_freq(void); */ #define CONFIG_ENABLE_36BIT_PHYS 1 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_ADDR_MAP +#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ +#endif + #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ #define CONFIG_SYS_MEMTEST_END 0x00400000 @@ -81,7 +74,7 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR /* DDR Setup */ -#define CONFIG_FSL_DDR2 +#define CONFIG_SYS_FSL_DDR2 #undef CONFIG_FSL_DDR_INTERACTIVE #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ #define CONFIG_DDR_SPD @@ -106,6 +99,37 @@ extern unsigned long get_clock_freq(void); #endif #undef CONFIG_CLOCKS_IN_MHZ +/* + * Physical Address Map + * + * 32bit: + * 0x0000_0000 0x7fff_ffff DDR 2G cacheable + * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M cacheable + * 0xa000_0000 0xbfff_ffff PCIe MEM 512M cacheable + * 0xc000_0000 0xdfff_ffff RapidIO 512M cacheable + * 0xe000_0000 0xe00f_ffff CCSR 1M non-cacheable + * 0xe200_0000 0xe20f_ffff PCI1 IO 1M non-cacheable + * 0xe300_0000 0xe30f_ffff PCIe IO 1M non-cacheable + * 0xf000_0000 0xf3ff_ffff SDRAM 64M cacheable + * 0xf800_0000 0xf80f_ffff NVRAM/CADMUS 1M non-cacheable + * 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M non-cacheable + * 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M non-cacheable + * + * 36bit: + * 0x00000_0000 0x07fff_ffff DDR 2G cacheable + * 0xc0000_0000 0xc1fff_ffff PCI1 MEM 512M cacheable + * 0xc2000_0000 0xc3fff_ffff PCIe MEM 512M cacheable + * 0xc4000_0000 0xc5fff_ffff RapidIO 512M cacheable + * 0xfe000_0000 0xfe00f_ffff CCSR 1M non-cacheable + * 0xfe200_0000 0xfe20f_ffff PCI1 IO 1M non-cacheable + * 0xfe300_0000 0xfe30f_ffff PCIe IO 1M non-cacheable + * 0xff000_0000 0xff3ff_ffff SDRAM 64M cacheable + * 0xff800_0000 0xff80f_ffff NVRAM/CADMUS 1M non-cacheable + * 0xfff00_0000 0xfff7f_ffff FLASH (2nd bank) 8M non-cacheable + * 0xfff80_0000 0xfffff_ffff FLASH (boot bank) 8M non-cacheable + * + */ + /* * Local Bus Definitions @@ -141,16 +165,23 @@ extern unsigned long get_clock_freq(void); * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx */ -#define CONFIG_SYS_BOOT_BLOCK 0xff000000 /* boot TLB block */ -#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_BOOT_BLOCK /* start of FLASH 16M */ +#define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */ +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_FLASH_BASE_PHYS 0xfff000000ull +#else +#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE +#endif -#define CONFIG_SYS_BR0_PRELIM 0xff801001 -#define CONFIG_SYS_BR1_PRELIM 0xff001001 +#define CONFIG_SYS_BR0_PRELIM \ + (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x800000) | BR_PS_16 | BR_V) +#define CONFIG_SYS_BR1_PRELIM \ + (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) #define CONFIG_SYS_OR0_PRELIM 0xff806e65 #define CONFIG_SYS_OR1_PRELIM 0xff806e65 -#define CONFIG_SYS_FLASH_BANKS_LIST {0xff800000, CONFIG_SYS_FLASH_BASE} +#define CONFIG_SYS_FLASH_BANKS_LIST \ + {CONFIG_SYS_FLASH_BASE_PHYS + 0x800000, CONFIG_SYS_FLASH_BASE_PHYS} #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */ #undef CONFIG_SYS_FLASH_CHECKSUM @@ -168,12 +199,12 @@ extern unsigned long get_clock_freq(void); /* * SDRAM on the Local Bus */ -#define CONFIG_SYS_LBC_CACHE_BASE 0xf0000000 /* Localbus cacheable */ -#define CONFIG_SYS_LBC_CACHE_SIZE 64 -#define CONFIG_SYS_LBC_NONCACHE_BASE 0xf8000000 /* Localbus non-cacheable */ -#define CONFIG_SYS_LBC_NONCACHE_SIZE 64 - -#define CONFIG_SYS_LBC_SDRAM_BASE CONFIG_SYS_LBC_CACHE_BASE /* Localbus SDRAM */ +#define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_LBC_SDRAM_BASE_PHYS 0xff0000000ull +#else +#define CONFIG_SYS_LBC_SDRAM_BASE_PHYS CONFIG_SYS_LBC_SDRAM_BASE +#endif #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ /* @@ -194,7 +225,9 @@ extern unsigned long get_clock_freq(void); * FIXME: the top 17 bits of BR2. */ -#define CONFIG_SYS_BR2_PRELIM 0xf0001861 +#define CONFIG_SYS_BR2_PRELIM \ + (BR_PHYS_ADDR(CONFIG_SYS_LBC_SDRAM_BASE_PHYS) \ + | BR_PS_32 | (3< " -#endif /* pass open firmware flat tree */ #define CONFIG_OF_LIBFDT 1 @@ -307,13 +341,12 @@ extern unsigned long get_clock_freq(void); /* * I2C */ -#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ -#define CONFIG_HARD_I2C /* I2C with hardware support*/ -#undef CONFIG_SOFT_I2C /* I2C bit-banged */ -#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CONFIG_SYS_I2C_SLAVE 0x7F -#define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */ -#define CONFIG_SYS_I2C_OFFSET 0x3000 +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_FSL +#define CONFIG_SYS_FSL_I2C_SPEED 400000 +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 +#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } /* EEPROM */ #define CONFIG_ID_EEPROM @@ -326,47 +359,54 @@ extern unsigned long get_clock_freq(void); * General PCI * Memory space is mapped 1-1, but I/O space must start from 0. */ -#define CONFIG_SYS_PCI_VIRT 0x80000000 /* 1G PCI TLB */ -#define CONFIG_SYS_PCI_PHYS 0x80000000 /* 1G PCI TLB */ - #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCI1_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCI1_MEM_PHYS 0xc00000000ull +#else #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 +#endif #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCI1_IO_PHYS 0xfe2000000ull +#else #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 -#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ - -#ifdef CONFIG_PCI2 -#define CONFIG_SYS_PCI2_MEM_VIRT 0xa0000000 -#define CONFIG_SYS_PCI2_MEM_BUS 0xa0000000 -#define CONFIG_SYS_PCI2_MEM_PHYS 0xa0000000 -#define CONFIG_SYS_PCI2_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCI2_IO_VIRT 0xe2800000 -#define CONFIG_SYS_PCI2_IO_BUS 0x00000000 -#define CONFIG_SYS_PCI2_IO_PHYS 0xe2800000 -#define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */ #endif +#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ #ifdef CONFIG_PCIE1 #define CONFIG_SYS_PCIE1_NAME "Slot" #define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc20000000ull +#else #define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000 +#endif #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_PCIE1_IO_VIRT 0xe3000000 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCIE1_IO_PHYS 0xfe3000000ull +#else #define CONFIG_SYS_PCIE1_IO_PHYS 0xe3000000 +#endif #define CONFIG_SYS_PCIE1_IO_SIZE 0x00100000 /* 1M */ #endif /* * RapidIO MMU */ -#define CONFIG_SYS_SRIO1_MEM_VIRT 0xC0000000 -#define CONFIG_SYS_SRIO1_MEM_BUS 0xC0000000 -#define CONFIG_SYS_SRIO1_MEM_PHYS CONFIG_SYS_SRIO1_MEM_BUS +#define CONFIG_SYS_SRIO1_MEM_VIRT 0xc0000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_SRIO1_MEM_PHYS 0xc40000000ull +#else +#define CONFIG_SYS_SRIO1_MEM_PHYS 0xc0000000 +#endif #define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 512M */ #ifdef CONFIG_LEGACY @@ -403,6 +443,8 @@ extern unsigned long get_clock_freq(void); #define CONFIG_TSEC4_NAME "eTSEC3" #undef CONFIG_MPC85XX_FEC +#define CONFIG_PHY_MARVELL + #define TSEC1_PHY_ADDR 0 #define TSEC2_PHY_ADDR 1 #define TSEC3_PHY_ADDR 2 @@ -473,7 +515,6 @@ extern unsigned long get_clock_freq(void); #define CONFIG_CMDLINE_EDITING /* Command-line editing */ #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ #if defined(CONFIG_CMD_KGDB) #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ #else @@ -482,7 +523,6 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ /* * For booting Linux, the board info and command line data @@ -494,7 +534,6 @@ extern unsigned long get_clock_freq(void); #if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif /* @@ -516,8 +555,8 @@ extern unsigned long get_clock_freq(void); #define CONFIG_IPADDR 192.168.1.253 #define CONFIG_HOSTNAME unknown -#define CONFIG_ROOTPATH /nfsroot -#define CONFIG_BOOTFILE 8548cds/uImage.uboot +#define CONFIG_ROOTPATH "/nfsroot" +#define CONFIG_BOOTFILE "8548cds/uImage.uboot" #define CONFIG_UBOOTPATH 8548cds/u-boot.bin /* TFTP server */ #define CONFIG_SERVERIP 192.168.1.1 @@ -534,13 +573,18 @@ extern unsigned long get_clock_freq(void); #define CONFIG_EXTRA_ENV_SETTINGS \ "hwconfig=fsl_ddr:ecc=off\0" \ "netdev=eth0\0" \ - "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ + "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ "tftpflash=tftpboot $loadaddr $uboot; " \ - "protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ - "erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ - "cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; " \ - "protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ - "cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0"\ + "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ + " +$filesize; " \ + "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ + " +$filesize; " \ + "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ + " $filesize; " \ + "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ + " +$filesize; " \ + "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ + " $filesize\0" \ "consoledev=ttyS1\0" \ "ramdiskaddr=2000000\0" \ "ramdiskfile=ramdisk.uboot\0" \