X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;ds=sidebyside;f=board%2Fsandburst%2Fcommon%2Fsb_common.c;h=6b910743d52fc5f8a8c3822a9d0e09e8fce266eb;hb=bb3bcfa2426cc6a0aecec7270e3ee67ca843a125;hp=d8b0564b3be93901e2faae1067c5144432fe8c54;hpb=d1c3b27525b664e8c4db6bb173eed51bfc8220de;p=platform%2Fkernel%2Fu-boot.git

diff --git a/board/sandburst/common/sb_common.c b/board/sandburst/common/sb_common.c
index d8b0564..6b91074 100644
--- a/board/sandburst/common/sb_common.c
+++ b/board/sandburst/common/sb_common.c
@@ -266,11 +266,11 @@ long int fixed_sdram (void)
 	/*--------------------------------------------------------------------
 	 * Setup some default
 	 *------------------------------------------------------------------*/
-	mtsdram (mem_uabba, 0x00000000);	/* ubba=0 (default)		*/
-	mtsdram (mem_slio, 0x00000000);		/* rdre=0 wrre=0 rarw=0		*/
-	mtsdram (mem_devopt, 0x00000000);	/* dll=0 ds=0 (normal)		*/
-	mtsdram (mem_wddctr, 0x00000000);	/* wrcp=0 dcd=0			*/
-	mtsdram (mem_clktr, 0x40000000);	/* clkp=1 (90 deg wr) dcdt=0	*/
+	mtsdram (SDRAM0_UABBA, 0x00000000);	/* ubba=0 (default)		*/
+	mtsdram (SDRAM0_SLIO, 0x00000000);		/* rdre=0 wrre=0 rarw=0		*/
+	mtsdram (SDRAM0_DEVOPT, 0x00000000);	/* dll=0 ds=0 (normal)		*/
+	mtsdram (SDRAM0_WDDCTR, 0x00000000);	/* wrcp=0 dcd=0			*/
+	mtsdram (SDRAM0_CLKTR, 0x40000000);	/* clkp=1 (90 deg wr) dcdt=0	*/
 
 	/*--------------------------------------------------------------------
 	 * Setup for board-specific specific mem
@@ -278,20 +278,20 @@ long int fixed_sdram (void)
 	/*
 	 * Following for CAS Latency = 2.5 @ 133 MHz PLB
 	 */
-	mtsdram (mem_b0cr, 0x000a4001); /* SDBA=0x000 128MB, Mode 3, enabled */
-	mtsdram (mem_tr0, 0x410a4012);	/* WR=2	 WD=1 CL=2.5 PA=3 CP=4 LD=2 */
+	mtsdram (SDRAM0_B0CR, 0x000a4001); /* SDBA=0x000 128MB, Mode 3, enabled */
+	mtsdram (SDRAM0_TR0, 0x410a4012);	/* WR=2	 WD=1 CL=2.5 PA=3 CP=4 LD=2 */
 	/* RA=10 RD=3			    */
-	mtsdram (mem_tr1, 0x8080082f);	/* SS=T2 SL=STAGE 3 CD=1 CT=0x02f   */
-	mtsdram (mem_rtr, 0x08200000);	/* Rate 15.625 ns @ 133 MHz PLB	    */
-	mtsdram (mem_cfg1, 0x00000000); /* Self-refresh exit, disable PM    */
+	mtsdram (SDRAM0_TR1, 0x8080082f);	/* SS=T2 SL=STAGE 3 CD=1 CT=0x02f   */
+	mtsdram (SDRAM0_RTR, 0x08200000);	/* Rate 15.625 ns @ 133 MHz PLB	    */
+	mtsdram (SDRAM0_CFG1, 0x00000000); /* Self-refresh exit, disable PM    */
 	udelay (400);			/* Delay 200 usecs (min)	    */
 
 	/*--------------------------------------------------------------------
 	 * Enable the controller, then wait for DCEN to complete
 	 *------------------------------------------------------------------*/
-	mtsdram (mem_cfg0, 0x86000000); /* DCEN=1, PMUD=1, 64-bit	    */
+	mtsdram (SDRAM0_CFG0, 0x86000000); /* DCEN=1, PMUD=1, 64-bit	    */
 	for (;;) {
-		mfsdram (mem_mcsts, reg);
+		mfsdram (SDRAM0_MCSTS, reg);
 		if (reg & 0x80000000)
 			break;
 	}
@@ -300,91 +300,6 @@ long int fixed_sdram (void)
 }
 #endif	/* !defined(CONFIG_SPD_EEPROM) */
 
-
-/*************************************************************************
- *  pci_pre_init
- *
- *  This routine is called just prior to registering the hose and gives
- *  the board the opportunity to check things. Returning a value of zero
- *  indicates that things are bad & PCI initialization should be aborted.
- *
- *	Different boards may wish to customize the pci controller structure
- *	(add regions, override default access routines, etc) or perform
- *	certain pre-initialization actions.
- *
- ************************************************************************/
-#if defined(CONFIG_PCI)
-int pci_pre_init(struct pci_controller * hose )
-{
-	unsigned long strap;
-
-	/*--------------------------------------------------------------------------+
-	 *	The metrobox is always configured as the host & requires the
-	 *	PCI arbiter to be enabled.
-	 *--------------------------------------------------------------------------*/
-	mfsdr(SDR0_SDSTP1, strap);
-	if( (strap & SDR0_SDSTP1_PAE_MASK) == 0 ){
-		printf("PCI: SDR0_STRP1[%08lX] - PCI Arbiter disabled.\n",strap);
-		return 0;
-	}
-
-	return 1;
-}
-#endif /* defined(CONFIG_PCI) */
-
-/*************************************************************************
- *  pci_target_init
- *
- *	The bootstrap configuration provides default settings for the pci
- *	inbound map (PIM). But the bootstrap config choices are limited and
- *	may not be sufficient for a given board.
- *
- ************************************************************************/
-#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
-void pci_target_init(struct pci_controller * hose )
-{
-	/*--------------------------------------------------------------------------+
-	 * Disable everything
-	 *--------------------------------------------------------------------------*/
-	out32r( PCIX0_PIM0SA, 0 ); /* disable */
-	out32r( PCIX0_PIM1SA, 0 ); /* disable */
-	out32r( PCIX0_PIM2SA, 0 ); /* disable */
-	out32r( PCIX0_EROMBA, 0 ); /* disable expansion rom */
-
-	/*--------------------------------------------------------------------------+
-	 * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping
-	 * options to not support sizes such as 128/256 MB.
-	 *--------------------------------------------------------------------------*/
-	out32r( PCIX0_PIM0LAL, CONFIG_SYS_SDRAM_BASE );
-	out32r( PCIX0_PIM0LAH, 0 );
-	out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 );
-
-	out32r( PCIX0_BAR0, 0 );
-
-	/*--------------------------------------------------------------------------+
-	 * Program the board's subsystem id/vendor id
-	 *--------------------------------------------------------------------------*/
-	out16r( PCIX0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID );
-	out16r( PCIX0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID );
-
-	out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY );
-}
-#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
-
-
-/*************************************************************************
- *  is_pci_host
- *
- *
- ************************************************************************/
-#if defined(CONFIG_PCI)
-int is_pci_host(struct pci_controller *hose)
-{
-    /* The metrobox is always configured as host. */
-    return(1);
-}
-#endif /* defined(CONFIG_PCI) */
-
 /*************************************************************************
  *  board_get_enetaddr
  *