X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;ds=sidebyside;f=board%2Ffreescale%2Fls2080ardb%2Feth_ls2080rdb.c;h=7034bc6e5d21465f8683e84a6a617c78ab369a62;hb=6cc04547cb3bbd3a3d78947f200acbae19e3c67f;hp=32677f7ae1b466f4d6e3f65b615d3f3e6c51c235;hpb=b9eaeae19eb93993e18149f119fa360b13c5643f;p=platform%2Fkernel%2Fu-boot.git

diff --git a/board/freescale/ls2080ardb/eth_ls2080rdb.c b/board/freescale/ls2080ardb/eth_ls2080rdb.c
index 32677f7..7034bc6 100644
--- a/board/freescale/ls2080ardb/eth_ls2080rdb.c
+++ b/board/freescale/ls2080ardb/eth_ls2080rdb.c
@@ -1,18 +1,19 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright 2015 Freescale Semiconductor, Inc.
  *
- *
- * SPDX-License-Identifier:     GPL-2.0+
  */
 
 #include <common.h>
 #include <command.h>
+#include <net.h>
 #include <netdev.h>
 #include <malloc.h>
 #include <fsl_mdio.h>
 #include <miiphy.h>
 #include <phy.h>
 #include <fm_eth.h>
+#include <asm/global_data.h>
 #include <asm/io.h>
 #include <exports.h>
 #include <asm/arch/fsl_serdes.h>
@@ -21,13 +22,14 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-int board_eth_init(bd_t *bis)
+int board_eth_init(struct bd_info *bis)
 {
+#ifndef CONFIG_DM_ETH
 #if defined(CONFIG_FSL_MC_ENET)
 	int i, interface;
 	struct memac_mdio_info mdio_info;
 	struct mii_dev *dev;
-	struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+	struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
 	u32 srds_s1;
 	struct memac_mdio_controller *reg;
 
@@ -35,14 +37,14 @@ int board_eth_init(bd_t *bis)
 				FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK;
 	srds_s1 >>= FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
 
-	reg = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO1;
+	reg = (struct memac_mdio_controller *)CFG_SYS_FSL_WRIOP1_MDIO1;
 	mdio_info.regs = reg;
 	mdio_info.name = DEFAULT_WRIOP_MDIO1_NAME;
 
 	/* Register the EMI 1 */
 	fm_memac_mdio_init(bis, &mdio_info);
 
-	reg = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO2;
+	reg = (struct memac_mdio_controller *)CFG_SYS_FSL_WRIOP1_MDIO2;
 	mdio_info.regs = reg;
 	mdio_info.name = DEFAULT_WRIOP_MDIO2_NAME;
 
@@ -51,21 +53,21 @@ int board_eth_init(bd_t *bis)
 
 	switch (srds_s1) {
 	case 0x2A:
-		wriop_set_phy_address(WRIOP1_DPMAC1, CORTINA_PHY_ADDR1);
-		wriop_set_phy_address(WRIOP1_DPMAC2, CORTINA_PHY_ADDR2);
-		wriop_set_phy_address(WRIOP1_DPMAC3, CORTINA_PHY_ADDR3);
-		wriop_set_phy_address(WRIOP1_DPMAC4, CORTINA_PHY_ADDR4);
-		wriop_set_phy_address(WRIOP1_DPMAC5, AQ_PHY_ADDR1);
-		wriop_set_phy_address(WRIOP1_DPMAC6, AQ_PHY_ADDR2);
-		wriop_set_phy_address(WRIOP1_DPMAC7, AQ_PHY_ADDR3);
-		wriop_set_phy_address(WRIOP1_DPMAC8, AQ_PHY_ADDR4);
+		wriop_set_phy_address(WRIOP1_DPMAC1, 0, CORTINA_PHY_ADDR1);
+		wriop_set_phy_address(WRIOP1_DPMAC2, 0, CORTINA_PHY_ADDR2);
+		wriop_set_phy_address(WRIOP1_DPMAC3, 0, CORTINA_PHY_ADDR3);
+		wriop_set_phy_address(WRIOP1_DPMAC4, 0, CORTINA_PHY_ADDR4);
+		wriop_set_phy_address(WRIOP1_DPMAC5, 0, AQ_PHY_ADDR1);
+		wriop_set_phy_address(WRIOP1_DPMAC6, 0, AQ_PHY_ADDR2);
+		wriop_set_phy_address(WRIOP1_DPMAC7, 0, AQ_PHY_ADDR3);
+		wriop_set_phy_address(WRIOP1_DPMAC8, 0, AQ_PHY_ADDR4);
 
 		break;
 	case 0x4B:
-		wriop_set_phy_address(WRIOP1_DPMAC1, CORTINA_PHY_ADDR1);
-		wriop_set_phy_address(WRIOP1_DPMAC2, CORTINA_PHY_ADDR2);
-		wriop_set_phy_address(WRIOP1_DPMAC3, CORTINA_PHY_ADDR3);
-		wriop_set_phy_address(WRIOP1_DPMAC4, CORTINA_PHY_ADDR4);
+		wriop_set_phy_address(WRIOP1_DPMAC1, 0, CORTINA_PHY_ADDR1);
+		wriop_set_phy_address(WRIOP1_DPMAC2, 0, CORTINA_PHY_ADDR2);
+		wriop_set_phy_address(WRIOP1_DPMAC3, 0, CORTINA_PHY_ADDR3);
+		wriop_set_phy_address(WRIOP1_DPMAC4, 0, CORTINA_PHY_ADDR4);
 
 		break;
 	default:
@@ -99,6 +101,7 @@ int board_eth_init(bd_t *bis)
 
 	cpu_eth_init(bis);
 #endif /* CONFIG_FSL_MC_ENET */
+#endif /* !CONFIG_DM_ETH */
 
 #ifdef CONFIG_PHY_AQUANTIA
 	/*
@@ -112,7 +115,12 @@ int board_eth_init(bd_t *bis)
 	gd->jt->mdio_phydev_for_ethname = mdio_phydev_for_ethname;
 	gd->jt->miiphy_set_current_dev = miiphy_set_current_dev;
 #endif
+
+#ifdef CONFIG_DM_ETH
+	return 0;
+#else
 	return pci_eth_init(bis);
+#endif
 }
 
 #if defined(CONFIG_RESET_PHY_R)