X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;ds=sidebyside;f=board%2Ffreescale%2Fls1043aqds%2Fls1043aqds.c;h=b02f649910f69be2afb8b8a0b04be00df6494a42;hb=6cc04547cb3bbd3a3d78947f200acbae19e3c67f;hp=941dfbc447ebe9f1b3ed29c1d8e7bc1710dee264;hpb=499a950d41879020a186627874cf7aa856112ca5;p=platform%2Fkernel%2Fu-boot.git diff --git a/board/freescale/ls1043aqds/ls1043aqds.c b/board/freescale/ls1043aqds/ls1043aqds.c index 941dfbc..b02f649 100644 --- a/board/freescale/ls1043aqds/ls1043aqds.c +++ b/board/freescale/ls1043aqds/ls1043aqds.c @@ -1,26 +1,35 @@ +// SPDX-License-Identifier: GPL-2.0+ /* * Copyright 2015 Freescale Semiconductor, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ + * Copyright 2019-2020 NXP */ #include +#include #include #include +#include +#include +#include +#include #include #include #include +#include #include +#include +#include #include +#include #include #include #include #include #include -#include #include #include #include +#include "../common/i2c_mux.h" #include "../common/qixis.h" #include "ls1043aqds_qixis.h" @@ -44,8 +53,135 @@ enum { #define CFG_UART_MUX_SHIFT 1 #define CFG_LPUART_EN 0x1 +#ifdef CONFIG_TFABOOT +struct ifc_regs ifc_cfg_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = { + { + "nor0", + CONFIG_SYS_NOR0_CSPR, + CONFIG_SYS_NOR0_CSPR_EXT, + CONFIG_SYS_NOR_AMASK, + CONFIG_SYS_NOR_CSOR, + { + CONFIG_SYS_NOR_FTIM0, + CONFIG_SYS_NOR_FTIM1, + CONFIG_SYS_NOR_FTIM2, + CONFIG_SYS_NOR_FTIM3 + }, + + }, + { + "nor1", + CONFIG_SYS_NOR1_CSPR, + CONFIG_SYS_NOR1_CSPR_EXT, + CONFIG_SYS_NOR_AMASK, + CONFIG_SYS_NOR_CSOR, + { + CONFIG_SYS_NOR_FTIM0, + CONFIG_SYS_NOR_FTIM1, + CONFIG_SYS_NOR_FTIM2, + CONFIG_SYS_NOR_FTIM3 + }, + }, + { + "nand", + CONFIG_SYS_NAND_CSPR, + CONFIG_SYS_NAND_CSPR_EXT, + CONFIG_SYS_NAND_AMASK, + CONFIG_SYS_NAND_CSOR, + { + CONFIG_SYS_NAND_FTIM0, + CONFIG_SYS_NAND_FTIM1, + CONFIG_SYS_NAND_FTIM2, + CONFIG_SYS_NAND_FTIM3 + }, + }, + { + "fpga", + CONFIG_SYS_FPGA_CSPR, + CONFIG_SYS_FPGA_CSPR_EXT, + CONFIG_SYS_FPGA_AMASK, + CONFIG_SYS_FPGA_CSOR, + { + CONFIG_SYS_FPGA_FTIM0, + CONFIG_SYS_FPGA_FTIM1, + CONFIG_SYS_FPGA_FTIM2, + CONFIG_SYS_FPGA_FTIM3 + }, + } +}; + +struct ifc_regs ifc_cfg_nand_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = { + { + "nand", + CONFIG_SYS_NAND_CSPR, + CONFIG_SYS_NAND_CSPR_EXT, + CONFIG_SYS_NAND_AMASK, + CONFIG_SYS_NAND_CSOR, + { + CONFIG_SYS_NAND_FTIM0, + CONFIG_SYS_NAND_FTIM1, + CONFIG_SYS_NAND_FTIM2, + CONFIG_SYS_NAND_FTIM3 + }, + }, + { + "nor0", + CONFIG_SYS_NOR0_CSPR, + CONFIG_SYS_NOR0_CSPR_EXT, + CONFIG_SYS_NOR_AMASK, + CONFIG_SYS_NOR_CSOR, + { + CONFIG_SYS_NOR_FTIM0, + CONFIG_SYS_NOR_FTIM1, + CONFIG_SYS_NOR_FTIM2, + CONFIG_SYS_NOR_FTIM3 + }, + }, + { + "nor1", + CONFIG_SYS_NOR1_CSPR, + CONFIG_SYS_NOR1_CSPR_EXT, + CONFIG_SYS_NOR_AMASK, + CONFIG_SYS_NOR_CSOR, + { + CONFIG_SYS_NOR_FTIM0, + CONFIG_SYS_NOR_FTIM1, + CONFIG_SYS_NOR_FTIM2, + CONFIG_SYS_NOR_FTIM3 + }, + }, + { + "fpga", + CONFIG_SYS_FPGA_CSPR, + CONFIG_SYS_FPGA_CSPR_EXT, + CONFIG_SYS_FPGA_AMASK, + CONFIG_SYS_FPGA_CSOR, + { + CONFIG_SYS_FPGA_FTIM0, + CONFIG_SYS_FPGA_FTIM1, + CONFIG_SYS_FPGA_FTIM2, + CONFIG_SYS_FPGA_FTIM3 + }, + } +}; + +void ifc_cfg_boot_info(struct ifc_regs_info *regs_info) +{ + enum boot_src src = get_boot_src(); + + if (src == BOOT_SOURCE_IFC_NAND) + regs_info->regs = ifc_cfg_nand_boot; + else + regs_info->regs = ifc_cfg_nor_boot; + regs_info->cs_size = CONFIG_SYS_FSL_IFC_BANK_COUNT; +} +#endif + int checkboard(void) { +#ifdef CONFIG_TFABOOT + enum boot_src src = get_boot_src(); +#endif char buf[64]; #ifndef CONFIG_SD_BOOT u8 sw; @@ -53,6 +189,12 @@ int checkboard(void) puts("Board: LS1043AQDS, boot from "); +#ifdef CONFIG_TFABOOT + if (src == BOOT_SOURCE_SD_MMC) + puts("SD\n"); + else { +#endif + #ifdef CONFIG_SD_BOOT puts("SD\n"); #else @@ -71,6 +213,9 @@ int checkboard(void) printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH); #endif +#ifdef CONFIG_TFABOOT + } +#endif printf("Sys ID: 0x%02x, Sys Ver: 0x%02x\n", QIXIS_READ(id), QIXIS_READ(arch)); @@ -132,44 +277,105 @@ unsigned long get_board_ddr_clk(void) return 66666666; } -int select_i2c_ch_pca9547(u8 ch) -{ - int ret; - - ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1); - if (ret) { - puts("PCA: failed to select proper channel\n"); - return ret; - } - - return 0; -} - int dram_init(void) { /* * When resuming from deep sleep, the I2C channel may not be * in the default channel. So, switch to the default channel * before accessing DDR SPD. + * + * PCA9547 mount on I2C1 bus */ - select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); - gd->ram_size = initdram(0); + select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0); + fsl_initdram(); +#if (!defined(CONFIG_SPL) && !defined(CONFIG_TFABOOT)) || \ + defined(CONFIG_SPL_BUILD) + /* This will break-before-make MMU for DDR */ + update_early_mmu_table(); +#endif return 0; } int i2c_multiplexer_select_vid_channel(u8 channel) { - return select_i2c_ch_pca9547(channel); + return select_i2c_ch_pca9547(channel, 0); } void board_retimer_init(void) { u8 reg; + int bus_num = 0; /* Retimer is connected to I2C1_CH7_CH5 */ - select_i2c_ch_pca9547(I2C_MUX_CH7); + select_i2c_ch_pca9547(I2C_MUX_CH7, bus_num); reg = I2C_MUX_CH5; +#if CONFIG_IS_ENABLED(DM_I2C) + struct udevice *dev; + int ret; + + ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_PCA_ADDR_SEC, + 1, &dev); + if (ret) { + printf("%s: Cannot find udev for a bus %d\n", __func__, + bus_num); + return; + } + dm_i2c_write(dev, 0, ®, 1); + + /* Access to Control/Shared register */ + ret = i2c_get_chip_for_busnum(bus_num, I2C_RETIMER_ADDR, + 1, &dev); + if (ret) { + printf("%s: Cannot find udev for a bus %d\n", __func__, + bus_num); + return; + } + + reg = 0x0; + dm_i2c_write(dev, 0xff, ®, 1); + + /* Read device revision and ID */ + dm_i2c_read(dev, 1, ®, 1); + debug("Retimer version id = 0x%x\n", reg); + + /* Enable Broadcast. All writes target all channel register sets */ + reg = 0x0c; + dm_i2c_write(dev, 0xff, ®, 1); + + /* Reset Channel Registers */ + dm_i2c_read(dev, 0, ®, 1); + reg |= 0x4; + dm_i2c_write(dev, 0, ®, 1); + + /* Enable override divider select and Enable Override Output Mux */ + dm_i2c_read(dev, 9, ®, 1); + reg |= 0x24; + dm_i2c_write(dev, 9, ®, 1); + + /* Select VCO Divider to full rate (000) */ + dm_i2c_read(dev, 0x18, ®, 1); + reg &= 0x8f; + dm_i2c_write(dev, 0x18, ®, 1); + + /* Selects active PFD MUX Input as Re-timed Data (001) */ + dm_i2c_read(dev, 0x1e, ®, 1); + reg &= 0x3f; + reg |= 0x20; + dm_i2c_write(dev, 0x1e, ®, 1); + + /* Set data rate as 10.3125 Gbps */ + reg = 0x0; + dm_i2c_write(dev, 0x60, ®, 1); + reg = 0xb2; + dm_i2c_write(dev, 0x61, ®, 1); + reg = 0x90; + dm_i2c_write(dev, 0x62, ®, 1); + reg = 0xb3; + dm_i2c_write(dev, 0x63, ®, 1); + reg = 0xcd; + dm_i2c_write(dev, 0x64, ®, 1); +#else i2c_write(I2C_MUX_PCA_ADDR_SEC, 0, 1, ®, 1); /* Access to Control/Shared register */ @@ -216,22 +422,29 @@ void board_retimer_init(void) i2c_write(I2C_RETIMER_ADDR, 0x63, 1, ®, 1); reg = 0xcd; i2c_write(I2C_RETIMER_ADDR, 0x64, 1, ®, 1); +#endif /* Return the default channel */ - select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); + select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, bus_num); } int board_early_init_f(void) { + u32 __iomem *cntcr = (u32 *)CFG_SYS_FSL_TIMER_ADDR; #ifdef CONFIG_HAS_FSL_XHCI_USB - struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; + struct ccsr_scfg *scfg = (struct ccsr_scfg *)CFG_SYS_FSL_SCFG_ADDR; u32 usb_pwrfault; #endif #ifdef CONFIG_LPUART u8 uart; #endif -#ifdef CONFIG_SYS_I2C_EARLY_INIT + /* + * Enable secure system counter for timer + */ + out_le32(cntcr, 0x1); + +#if defined(CONFIG_SYS_I2C_EARLY_INIT) i2c_early_init_f(); #endif fsl_lsch2_early_init_f(); @@ -262,7 +475,7 @@ int board_early_init_f(void) bool is_warm_boot(void) { #define DCFG_CCSR_CRSTSR_WDRFR (1 << 3) - struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR; + struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR; if (in_be32(&gur->crstsr) & DCFG_CCSR_CRSTSR_WDRFR) return 1; @@ -309,21 +522,26 @@ int misc_init_r(void) int board_init(void) { - select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); +#ifdef CONFIG_SYS_FSL_ERRATUM_A010315 + erratum_a010315(); +#endif + + select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0); board_retimer_init(); -#ifdef CONFIG_SYS_FSL_SERDES +#ifdef CFG_SYS_FSL_SERDES config_serdes_mux(); #endif -#ifdef CONFIG_LAYERSCAPE_NS_ACCESS - enable_layerscape_ns_access(); +#ifdef CONFIG_FSL_LS_PPA + ppa_init(); #endif + return 0; } #ifdef CONFIG_OF_BOARD_SETUP -int ft_board_setup(void *blob, bd_t *bd) +int ft_board_setup(void *blob, struct bd_info *bd) { u64 base[CONFIG_NR_DRAM_BANKS]; u64 size[CONFIG_NR_DRAM_BANKS]; @@ -338,11 +556,12 @@ int ft_board_setup(void *blob, bd_t *bd) fdt_fixup_memory_banks(blob, base, size, 2); ft_cpu_setup(blob, bd); -#ifdef CONFIG_SYS_DPAA_FMAN - fdt_fixup_fman_ethernet(blob); +#ifdef CONFIG_FMAN_ENET fdt_fixup_board_enet(blob); #endif + fdt_fixup_icid(blob); + reg = QIXIS_READ(brdcfg[0]); reg = (reg & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT; @@ -373,3 +592,10 @@ u16 flash_read16(void *addr) return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00); } + +#if defined(CONFIG_TFABOOT) && defined(CONFIG_ENV_IS_IN_SPI_FLASH) +void *env_sf_get_env_addr(void) +{ + return (void *)(CFG_SYS_FSL_QSPI_BASE + CONFIG_ENV_OFFSET); +} +#endif