#include <stdlib.h>
#include <stdio.h>
#include <string.h>
-#include <assert.h>
#include <fcntl.h>
#include <inttypes.h>
#include <errno.h>
#include <sys/stat.h>
#include <sys/time.h>
-#include "drm.h"
-#include "i915_drm.h"
+
+#include <drm.h>
+
+#include "ioctl_wrappers.h"
#include "drmtest.h"
-#include "intel_bufmgr.h"
-#include "intel_batchbuffer.h"
-#include "intel_gpu_tools.h"
+#include "intel_chipset.h"
+#include "intel_io.h"
#include "i830_reg.h"
+#include "igt_aux.h"
#define LOCAL_I915_EXEC_VEBOX (4<<0)
-bool skipped_all = true;
static drm_intel_bufmgr *bufmgr;
struct intel_batchbuffer *batch;
*/
#define COLOR 0xffffffff
-static void run_test(int ring, const char *testname)
+static void run_test(int ring)
{
uint32_t *ptr;
int i;
- skipped_all = false;
-
- printf("running subtest %s\n", testname);
+ gem_require_ring(fd, ring);
+ /* Testing render only makes sense with separate blt. */
+ if (ring == I915_EXEC_RENDER)
+ gem_require_ring(fd, I915_EXEC_BLT);
target_bo = drm_intel_bo_alloc(bufmgr, "target bo", 4096, 4096);
- if (!target_bo) {
- fprintf(stderr, "failed to alloc target buffer\n");
- exit(-1);
- }
+ igt_assert(target_bo);
/* Need to map first so that we can do our own domain mangement with
* set_domain. */
drm_intel_bo_map(target_bo, 0);
ptr = target_bo->virtual;
- assert(*ptr == 0);
+ igt_assert(*ptr == 0);
/* put some load onto the gpu to keep the light buffers active for long
* enough */
for (i = 0; i < 1000; i++) {
- BEGIN_BATCH(8);
- OUT_BATCH(XY_SRC_COPY_BLT_CMD |
- XY_SRC_COPY_BLT_WRITE_ALPHA |
- XY_SRC_COPY_BLT_WRITE_RGB);
+ BLIT_COPY_BATCH_START(batch->devid, 0);
OUT_BATCH((3 << 24) | /* 32 bits */
(0xcc << 16) | /* copy ROP */
4096);
OUT_BATCH(0); /* dst x1,y1 */
OUT_BATCH((1024 << 16) | 512);
OUT_RELOC(load_bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
+ BLIT_RELOC_UDW(batch->devid);
OUT_BATCH((0 << 16) | 512); /* src x1, y1 */
OUT_BATCH(4096);
OUT_RELOC(load_bo, I915_GEM_DOMAIN_RENDER, 0, 0);
+ BLIT_RELOC_UDW(batch->devid);
ADVANCE_BATCH();
}
- BEGIN_BATCH(6);
- OUT_BATCH(XY_COLOR_BLT_CMD |
- XY_COLOR_BLT_WRITE_ALPHA |
- XY_COLOR_BLT_WRITE_RGB);
+ COLOR_BLIT_COPY_BATCH_START(batch->devid, 0);
OUT_BATCH((3 << 24) | /* 32 bits */
(0xff << 16) |
128);
OUT_BATCH(0); /* dst x1,y1 */
OUT_BATCH((1 << 16) | 1);
OUT_RELOC(target_bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
+ BLIT_RELOC_UDW(batch->devid);
OUT_BATCH(COLOR);
ADVANCE_BATCH();
intel_batchbuffer_flush_on_ring(batch, ring);
gem_set_domain(fd, target_bo->handle, I915_GEM_DOMAIN_GTT, 0);
- assert(*ptr == COLOR);
+ igt_assert(*ptr == COLOR);
drm_intel_bo_unmap(target_bo);
drm_intel_bo_unreference(target_bo);
}
-static int has_ring(int ring)
-{
- switch (ring) {
- case I915_EXEC_RENDER: /* test only makes sense with separate blitter */
- return HAS_BLT_RING(intel_get_drm_devid(fd));
- case I915_EXEC_BSD:
- return HAS_BSD_RING(intel_get_drm_devid(fd));
- case LOCAL_I915_EXEC_VEBOX:
- return gem_has_vebox(fd);
- default:
- return 0;
- }
-}
-
-int main(int argc, char **argv)
+igt_main
{
static const struct {
const char *name;
};
int i;
- drmtest_subtest_init(argc, argv);
+ igt_skip_on_simulation();
- fd = drm_open_any();
+ igt_fixture {
+ fd = drm_open_any();
- /* Test requires MI_FLUSH_DW and MI_COND_BATCH_BUFFER_END */
- if (intel_gen(intel_get_drm_devid(fd)) < 6)
- return 77;
+ /* Test requires MI_FLUSH_DW and MI_COND_BATCH_BUFFER_END */
+ igt_require(intel_gen(intel_get_drm_devid(fd)) >= 6);
- bufmgr = drm_intel_bufmgr_gem_init(fd, 4096);
- if (!bufmgr) {
- fprintf(stderr, "failed to init libdrm\n");
- exit(-1);
- }
- /* don't enable buffer reuse!! */
- //drm_intel_bufmgr_gem_enable_reuse(bufmgr);
+ bufmgr = drm_intel_bufmgr_gem_init(fd, 4096);
+ igt_assert(bufmgr);
+ /* don't enable buffer reuse!! */
+ //drm_intel_bufmgr_gem_enable_reuse(bufmgr);
- batch = intel_batchbuffer_alloc(bufmgr, intel_get_drm_devid(fd));
- assert(batch);
+ batch = intel_batchbuffer_alloc(bufmgr, intel_get_drm_devid(fd));
+ igt_assert(batch);
- dummy_bo = drm_intel_bo_alloc(bufmgr, "dummy bo", 4096, 4096);
- if (!dummy_bo) {
- fprintf(stderr, "failed to alloc dummy buffer\n");
- exit(-1);
- }
+ dummy_bo = drm_intel_bo_alloc(bufmgr, "dummy bo", 4096, 4096);
+ igt_assert(dummy_bo);
- load_bo = drm_intel_bo_alloc(bufmgr, "load bo", 1024*4096, 4096);
- if (!load_bo) {
- fprintf(stderr, "failed to alloc load buffer\n");
- exit(-1);
+ load_bo = drm_intel_bo_alloc(bufmgr, "load bo", 1024*4096, 4096);
+ igt_assert(load_bo);
}
for (i = 0; i < ARRAY_SIZE(tests); i++) {
- if (has_ring(tests[i].ring) &&
- drmtest_run_subtest(tests[i].name))
- run_test(tests[i].ring, tests[i].name);
+ igt_subtest(tests[i].name)
+ run_test(tests[i].ring);
}
- drmtest_fork_signal_helper();
+ igt_fork_signal_helper();
for (i = 0; i < ARRAY_SIZE(tests); i++) {
- char name[180];
- snprintf(name, sizeof(name), "%s-interruptible", tests[i].name);
- if (has_ring(tests[i].ring) && drmtest_run_subtest(name))
- run_test(tests[i].ring, name);
+ igt_subtest_f("%s-interruptible", tests[i].name)
+ run_test(tests[i].ring);
}
- drmtest_stop_signal_helper();
-
- drm_intel_bufmgr_destroy(bufmgr);
+ igt_stop_signal_helper();
- close(fd);
+ igt_fixture {
+ drm_intel_bufmgr_destroy(bufmgr);
- return skipped_all ? 77 : 0;
+ close(fd);
+ }
}
projects / platform / upstream / intel-gpu-tools.git / blobdiff