#include <errno.h>
#include <sys/stat.h>
#include <sys/time.h>
-#include "drm.h"
-#include "i915_drm.h"
+
+#include <drm.h>
+
+#include "ioctl_wrappers.h"
#include "drmtest.h"
-#include "intel_bufmgr.h"
-#include "intel_batchbuffer.h"
-#include "intel_gpu_tools.h"
+#include "intel_chipset.h"
+#include "intel_io.h"
+#include "igt_aux.h"
/*
* Testcase: pwrite/pread consistency when touching partial cachelines
cmd_bits |= XY_SRC_COPY_BLT_SRC_TILED;
}
- BEGIN_BATCH(8);
- OUT_BATCH(XY_SRC_COPY_BLT_CMD |
- XY_SRC_COPY_BLT_WRITE_ALPHA |
- XY_SRC_COPY_BLT_WRITE_RGB |
- cmd_bits);
+ BLIT_COPY_BATCH_START(devid, cmd_bits);
OUT_BATCH((3 << 24) | /* 32 bits */
(0xcc << 16) | /* copy ROP */
dst_pitch);
{
int i, j;
- printf("checking partial reads\n");
for (i = 0; i < ROUNDS; i++) {
int start, len;
int val = i % 256;
drm_intel_bo_get_subdata(scratch_bo, start, len, tmp);
for (j = 0; j < len; j++) {
- if (tmp[j] != val) {
- printf("mismatch at %i, got: %i, expected: %i\n",
- start + j, tmp[j], val);
- exit(1);
- }
+ igt_assert_f(tmp[j] == val,
+ "mismatch at %i, got: %i, expected: %i\n",
+ start + j, tmp[j], val);
}
igt_progress("partial reads test: ", i, ROUNDS);
{
int i, j;
- printf("checking partial writes\n");
for (i = 0; i < ROUNDS; i++) {
int start, len;
int val = i % 256;
compare_tmp);
for (j = 0; j < start; j++) {
- if (compare_tmp[j] != val) {
- printf("amismatch at %i, got: %i, expected: %i\n",
- j, tmp[j], val);
- exit(1);
- }
+ igt_assert_f(compare_tmp[j] == val,
+ "mismatch at %i, got: %i, expected: %i\n",
+ j, tmp[j], val);
}
for (; j < start + len; j++) {
- if (compare_tmp[j] != tmp[0]) {
- printf("bmismatch at %i, got: %i, expected: %i\n",
- j, tmp[j], i);
- exit(1);
- }
+ igt_assert_f(compare_tmp[j] == tmp[0],
+ "mismatch at %i, got: %i, expected: %i\n",
+ j, tmp[j], i);
}
for (; j < BO_SIZE; j++) {
- if (compare_tmp[j] != val) {
- printf("cmismatch at %i, got: %i, expected: %i\n",
- j, tmp[j], val);
- exit(1);
- }
+ igt_assert_f(compare_tmp[j] == val,
+ "mismatch at %i, got: %i, expected: %i\n",
+ j, tmp[j], val);
}
drm_intel_gem_bo_unmap_gtt(staging_bo);
{
int i, j;
- printf("checking partial writes after partial reads\n");
for (i = 0; i < ROUNDS; i++) {
int start, len;
int val = i % 256;
drm_intel_bo_get_subdata(scratch_bo, start, len, tmp);
for (j = 0; j < len; j++) {
- if (tmp[j] != val) {
- printf("mismatch in read at %i, got: %i, expected: %i\n",
- start + j, tmp[j], val);
- exit(1);
- }
+ igt_assert_f(tmp[j] == val,
+ "mismatch in read at %i, got: %i, expected: %i\n",
+ start + j, tmp[j], val);
}
/* Change contents through gtt to make the pread cachelines
compare_tmp);
for (j = 0; j < start; j++) {
- if (compare_tmp[j] != val) {
- printf("mismatch at %i, got: %i, expected: %i\n",
- j, tmp[j], val);
- exit(1);
- }
+ igt_assert_f(compare_tmp[j] == val,
+ "mismatch at %i, got: %i, expected: %i\n",
+ j, tmp[j], val);
}
for (; j < start + len; j++) {
- if (compare_tmp[j] != tmp[0]) {
- printf("mismatch at %i, got: %i, expected: %i\n",
- j, tmp[j], tmp[0]);
- exit(1);
- }
+ igt_assert_f(compare_tmp[j] == tmp[0],
+ "mismatch at %i, got: %i, expected: %i\n",
+ j, tmp[j], tmp[0]);
}
for (; j < BO_SIZE; j++) {
- if (compare_tmp[j] != val) {
- printf("mismatch at %i, got: %i, expected: %i\n",
- j, tmp[j], val);
- exit(1);
- }
+ igt_assert_f(compare_tmp[j] == val,
+ "mismatch at %i, got: %i, expected: %i\n",
+ j, tmp[j], val);
}
drm_intel_gem_bo_unmap_gtt(staging_bo);
}
}
-int main(int argc, char **argv)
+igt_main
{
uint32_t tiling_mode = I915_TILING_X;
- igt_subtest_init(argc, argv);
igt_skip_on_simulation();
srandom(0xdeadbeef);
- fd = drm_open_any();
-
- bufmgr = drm_intel_bufmgr_gem_init(fd, 4096);
- //drm_intel_bufmgr_gem_enable_reuse(bufmgr);
- devid = intel_get_drm_devid(fd);
- batch = intel_batchbuffer_alloc(bufmgr, devid);
-
- /* overallocate the buffers we're actually using because */
- scratch_bo = drm_intel_bo_alloc_tiled(bufmgr, "scratch bo", 1024,
- BO_SIZE/4096, 4,
- &tiling_mode, &scratch_pitch, 0);
- igt_assert(tiling_mode == I915_TILING_X);
- igt_assert(scratch_pitch == 4096);
- staging_bo = drm_intel_bo_alloc(bufmgr, "staging bo", BO_SIZE, 4096);
- tiled_staging_bo = drm_intel_bo_alloc_tiled(bufmgr, "scratch bo", 1024,
- BO_SIZE/4096, 4,
- &tiling_mode,
- &scratch_pitch, 0);
-
- igt_init_aperture_trashers(bufmgr);
- mappable_gtt_limit = gem_mappable_aperture_size();
+ igt_fixture {
+ fd = drm_open_any();
+
+ bufmgr = drm_intel_bufmgr_gem_init(fd, 4096);
+ //drm_intel_bufmgr_gem_enable_reuse(bufmgr);
+ devid = intel_get_drm_devid(fd);
+ batch = intel_batchbuffer_alloc(bufmgr, devid);
+
+ /* overallocate the buffers we're actually using because */
+ scratch_bo = drm_intel_bo_alloc_tiled(bufmgr, "scratch bo", 1024,
+ BO_SIZE/4096, 4,
+ &tiling_mode, &scratch_pitch, 0);
+ igt_assert(tiling_mode == I915_TILING_X);
+ igt_assert(scratch_pitch == 4096);
+ staging_bo = drm_intel_bo_alloc(bufmgr, "staging bo", BO_SIZE, 4096);
+ tiled_staging_bo = drm_intel_bo_alloc_tiled(bufmgr, "scratch bo", 1024,
+ BO_SIZE/4096, 4,
+ &tiling_mode,
+ &scratch_pitch, 0);
+
+ igt_init_aperture_trashers(bufmgr);
+ mappable_gtt_limit = gem_mappable_aperture_size();
+ }
igt_subtest("reads")
test_partial_reads();
igt_subtest("writes-after-reads")
test_partial_read_writes();
- igt_cleanup_aperture_trashers();
- drm_intel_bufmgr_destroy(bufmgr);
+ igt_fixture {
+ igt_cleanup_aperture_trashers();
+ drm_intel_bufmgr_destroy(bufmgr);
- close(fd);
-
- return 0;
+ close(fd);
+ }
}
projects / platform / upstream / intel-gpu-tools.git / blobdiff