#include <sys/stat.h>
#include <sys/time.h>
#include "drm.h"
-#include "i915_drm.h"
+#include "ioctl_wrappers.h"
#include "drmtest.h"
#include "intel_bufmgr.h"
#include "intel_batchbuffer.h"
-#include "intel_gpu_tools.h"
+#include "intel_chipset.h"
+#include "intel_io.h"
static drm_intel_bufmgr *bufmgr;
struct intel_batchbuffer *batch;
igt_assert(target_bo);
if (preuse_buffer) {
- BEGIN_BATCH(6);
- OUT_BATCH(XY_COLOR_BLT_CMD | COLOR_BLT_WRITE_ALPHA | XY_COLOR_BLT_WRITE_RGB);
+ COLOR_BLIT_COPY_BATCH_START(devid, 0);
OUT_BATCH((3 << 24) | (0xf0 << 16) | 64);
OUT_BATCH(0);
OUT_BATCH(1 << 16 | 1);
OUT_RELOC(target_bo,
I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
0);
+ BLIT_RELOC_UDW(devid);
OUT_BATCH(0xdeadbeef);
ADVANCE_BATCH();
intel_batchbuffer_flush(batch);
- igt_assert(target_bo->offset != 0);
- } else
- igt_assert(target_bo->offset == 0);
+ }
/* gem_storedw_batches_loop.c is a bit overenthusiastic with
* creating new batchbuffers - with buffer reuse disabled, the
* support code will do that for us. */
- if (intel_gen(devid) >= 6) {
+ if (intel_gen(devid) >= 8) {
+ BEGIN_BATCH(5);
+ OUT_BATCH(GFX_OP_PIPE_CONTROL + 1);
+ OUT_BATCH(PIPE_CONTROL_WRITE_IMMEDIATE);
+ OUT_RELOC(target_bo,
+ I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
+ PIPE_CONTROL_GLOBAL_GTT);
+ BLIT_RELOC_UDW(devid);
+ OUT_BATCH(val); /* write data */
+ ADVANCE_BATCH();
+
+ } else if (intel_gen(devid) >= 6) {
/* work-around hw issue, see intel_emit_post_sync_nonzero_flush
* in mesa sources. */
BEGIN_BATCH(4);