#include <stdlib.h>
#include <stdio.h>
#include <string.h>
-#include <assert.h>
#include <fcntl.h>
#include <inttypes.h>
#include <errno.h>
#include <sys/stat.h>
#include <sys/time.h>
-#include "drm.h"
-#include "i915_drm.h"
+
+#include <drm.h>
+
+#include "ioctl_wrappers.h"
#include "drmtest.h"
#include "intel_bufmgr.h"
#include "intel_batchbuffer.h"
-#include "intel_gpu_tools.h"
+#include "intel_io.h"
+#include "intel_chipset.h"
+#include "igt_aux.h"
/*
* Testcase: snoop consistency when touching partial cachelines
static void
copy_bo(drm_intel_bo *src, drm_intel_bo *dst)
{
- BEGIN_BATCH(8);
- OUT_BATCH(XY_SRC_COPY_BLT_CMD |
- XY_SRC_COPY_BLT_WRITE_ALPHA |
- XY_SRC_COPY_BLT_WRITE_RGB);
+ BLIT_COPY_BATCH_START(devid, 0);
OUT_BATCH((3 << 24) | /* 32 bits */
(0xcc << 16) | /* copy ROP */
4096);
OUT_BATCH(0 << 16 | 0);
OUT_BATCH((BO_SIZE/4096) << 16 | 1024);
OUT_RELOC_FENCED(dst, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
+ BLIT_RELOC_UDW(devid);
OUT_BATCH(0 << 16 | 0);
OUT_BATCH(4096);
OUT_RELOC_FENCED(src, I915_GEM_DOMAIN_RENDER, 0, 0);
+ BLIT_RELOC_UDW(devid);
ADVANCE_BATCH();
intel_batchbuffer_flush(batch);
if (bo->offset < mappable_gtt_limit &&
(IS_G33(devid) || intel_gen(devid) >= 4))
- drmtest_trash_aperture();
+ igt_trash_aperture();
copy_bo(tmp_bo, bo);
}
#define TEST_READ 0x1
#define TEST_WRITE 0x2
#define TEST_BOTH (TEST_READ | TEST_WRITE)
-int main(int argc, char **argv)
+igt_main
{
unsigned flags = TEST_BOTH;
int i, j;
uint8_t *cpu_ptr;
uint8_t *gtt_ptr;
- drmtest_subtest_init(argc, argv);
- drmtest_skip_on_simulation();
+ igt_skip_on_simulation();
- srandom(0xdeadbeef);
+ igt_fixture {
+ srandom(0xdeadbeef);
- fd = drm_open_any();
+ fd = drm_open_any();
- gem_check_caching(fd);
+ gem_require_caching(fd);
- devid = intel_get_drm_devid(fd);
- if (IS_GEN2(devid)) /* chipset only handles cached -> uncached */
- flags &= ~TEST_READ;
- if (IS_BROADWATER(devid) || IS_CRESTLINE(devid)) {
- /* chipset is completely fubar */
- printf("coherency broken on i965g/gm\n");
- flags = 0;
- }
+ devid = intel_get_drm_devid(fd);
+ if (IS_GEN2(devid)) /* chipset only handles cached -> uncached */
+ flags &= ~TEST_READ;
+ if (IS_BROADWATER(devid) || IS_CRESTLINE(devid)) {
+ /* chipset is completely fubar */
+ igt_info("coherency broken on i965g/gm\n");
+ flags = 0;
+ }
- bufmgr = drm_intel_bufmgr_gem_init(fd, 4096);
- batch = intel_batchbuffer_alloc(bufmgr, devid);
+ bufmgr = drm_intel_bufmgr_gem_init(fd, 4096);
+ batch = intel_batchbuffer_alloc(bufmgr, devid);
- /* overallocate the buffers we're actually using because */
- scratch_bo = drm_intel_bo_alloc(bufmgr, "scratch bo", BO_SIZE, 4096);
- gem_set_caching(fd, scratch_bo->handle, 1);
+ /* overallocate the buffers we're actually using because */
+ scratch_bo = drm_intel_bo_alloc(bufmgr, "scratch bo", BO_SIZE, 4096);
+ gem_set_caching(fd, scratch_bo->handle, 1);
- staging_bo = drm_intel_bo_alloc(bufmgr, "staging bo", BO_SIZE, 4096);
+ staging_bo = drm_intel_bo_alloc(bufmgr, "staging bo", BO_SIZE, 4096);
- drmtest_init_aperture_trashers(bufmgr);
- mappable_gtt_limit = gem_mappable_aperture_size();
+ igt_init_aperture_trashers(bufmgr);
+ mappable_gtt_limit = gem_mappable_aperture_size();
+ }
- drmtest_subtest_block("reads") {
- if (!(flags & TEST_READ))
- drmtest_skip();
+ igt_subtest("reads") {
+ igt_require(flags & TEST_READ);
- printf("checking partial reads\n");
+ igt_info("checking partial reads\n");
for (i = 0; i < ROUNDS; i++) {
uint8_t val0 = i;
drm_intel_bo_map(scratch_bo, false);
cpu_ptr = scratch_bo->virtual;
for (j = 0; j < len; j++) {
- if (cpu_ptr[j] != val0) {
- printf("mismatch at %i, got: %i, expected: %i\n",
- j, cpu_ptr[j], val0);
- exit(1);
- }
+ igt_assert_f(cpu_ptr[j] == val0,
+ "mismatch at %i, got: %i, expected: %i\n",
+ j, cpu_ptr[j], val0);
}
drm_intel_bo_unmap(scratch_bo);
- drmtest_progress("partial reads test: ", i, ROUNDS);
+ igt_progress("partial reads test: ", i, ROUNDS);
}
}
- drmtest_subtest_block("writes") {
- if (!(flags & TEST_WRITE))
- drmtest_skip();
+ igt_subtest("writes") {
+ igt_require(flags & TEST_WRITE);
- printf("checking partial writes\n");
+ igt_info("checking partial writes\n");
for (i = 0; i < ROUNDS; i++) {
uint8_t val0 = i, val1;
gtt_ptr = staging_bo->virtual;
for (j = 0; j < start; j++) {
- if (gtt_ptr[j] != val0) {
- printf("mismatch at %i, partial=[%d+%d] got: %i, expected: %i\n",
- j, start, len, gtt_ptr[j], val0);
- exit(1);
- }
+ igt_assert_f(gtt_ptr[j] == val0,
+ "mismatch at %i, partial=[%d+%d] got: %i, expected: %i\n",
+ j, start, len, gtt_ptr[j], val0);
}
for (; j < start + len; j++) {
- if (gtt_ptr[j] != val1) {
- printf("mismatch at %i, partial=[%d+%d] got: %i, expected: %i\n",
- j, start, len, gtt_ptr[j], val1);
- exit(1);
- }
+ igt_assert_f(gtt_ptr[j] == val1,
+ "mismatch at %i, partial=[%d+%d] got: %i, expected: %i\n",
+ j, start, len, gtt_ptr[j], val1);
}
for (; j < BO_SIZE; j++) {
- if (gtt_ptr[j] != val0) {
- printf("mismatch at %i, partial=[%d+%d] got: %i, expected: %i\n",
- j, start, len, gtt_ptr[j], val0);
- exit(1);
- }
+ igt_assert_f(gtt_ptr[j] == val0,
+ "mismatch at %i, partial=[%d+%d] got: %i, expected: %i\n",
+ j, start, len, gtt_ptr[j], val0);
}
drm_intel_gem_bo_unmap_gtt(staging_bo);
- drmtest_progress("partial writes test: ", i, ROUNDS);
+ igt_progress("partial writes test: ", i, ROUNDS);
}
}
- drmtest_subtest_block("read-writes") {
- if (!((flags & TEST_BOTH) == TEST_BOTH))
- drmtest_skip();
+ igt_subtest("read-writes") {
+ igt_require((flags & TEST_BOTH) == TEST_BOTH);
- printf("checking partial writes after partial reads\n");
+ igt_info("checking partial writes after partial reads\n");
for (i = 0; i < ROUNDS; i++) {
uint8_t val0 = i, val1, val2;
do_or_die(drm_intel_bo_map(scratch_bo, false));
cpu_ptr = scratch_bo->virtual;
for (j = 0; j < len; j++) {
- if (cpu_ptr[j] != val0) {
- printf("mismatch in read at %i, got: %i, expected: %i\n",
- j, cpu_ptr[j], val0);
- exit(1);
- }
+ igt_assert_f(cpu_ptr[j] == val0,
+ "mismatch in read at %i, got: %i, expected: %i\n",
+ j, cpu_ptr[j], val0);
}
drm_intel_bo_unmap(scratch_bo);
gtt_ptr = staging_bo->virtual;
for (j = 0; j < start; j++) {
- if (gtt_ptr[j] != val1) {
- printf("mismatch at %i, partial=[%d+%d] got: %i, expected: %i\n",
- j, start, len, gtt_ptr[j], val1);
- exit(1);
- }
+ igt_assert_f(gtt_ptr[j] == val1,
+ "mismatch at %i, partial=[%d+%d] got: %i, expected: %i\n",
+ j, start, len, gtt_ptr[j], val1);
}
for (; j < start + len; j++) {
- if (gtt_ptr[j] != val2) {
- printf("mismatch at %i, partial=[%d+%d] got: %i, expected: %i\n",
- j, start, len, gtt_ptr[j], val2);
- exit(1);
- }
+ igt_assert_f(gtt_ptr[j] == val2,
+ "mismatch at %i, partial=[%d+%d] got: %i, expected: %i\n",
+ j, start, len, gtt_ptr[j], val2);
}
for (; j < BO_SIZE; j++) {
- if (gtt_ptr[j] != val1) {
- printf("mismatch at %i, partial=[%d+%d] got: %i, expected: %i\n",
- j, start, len, gtt_ptr[j], val1);
- exit(1);
- }
+ igt_assert_f(gtt_ptr[j] == val1,
+ "mismatch at %i, partial=[%d+%d] got: %i, expected: %i\n",
+ j, start, len, gtt_ptr[j], val1);
}
drm_intel_gem_bo_unmap_gtt(staging_bo);
drm_intel_bo_unmap(scratch_bo);
- drmtest_progress("partial read/writes test: ", i, ROUNDS);
+ igt_progress("partial read/writes test: ", i, ROUNDS);
}
}
- drmtest_cleanup_aperture_trashers();
- drm_intel_bufmgr_destroy(bufmgr);
-
- close(fd);
+ igt_fixture {
+ igt_cleanup_aperture_trashers();
+ drm_intel_bufmgr_destroy(bufmgr);
- return drmtest_retval();
+ close(fd);
+ }
}
projects / platform / upstream / intel-gpu-tools.git / blobdiff