Upstream version 10.39.225.0

[platform/framework/web/crosswalk.git] / src / v8 / src / mips64 / simulator-mips64.cc

diff --git a/src/v8/src/mips64/simulator-mips64.cc b/src/v8/src/mips64/simulator-mips64.cc
index c075584..4c74939 100644 (file)
--- a/src/v8/src/mips64/simulator-mips64.cc
+++ b/src/v8/src/mips64/simulator-mips64.cc
@@ -12,8 +12,8 @@
 #if V8_TARGET_ARCH_MIPS64
 
 #include "src/assembler.h"
+#include "src/base/bits.h"
 #include "src/disasm.h"
-#include "src/globals.h"    // Need the BitCast.
 #include "src/mips64/constants-mips64.h"
 #include "src/mips64/simulator-mips64.h"
 #include "src/ostreams.h"
@@ -1056,13 +1056,13 @@ void Simulator::set_fpu_register_hi_word(int fpureg, int32_t value) {
 
 void Simulator::set_fpu_register_float(int fpureg, float value) {
   DCHECK((fpureg >= 0) && (fpureg < kNumFPURegisters));
-  *BitCast<float*>(&FPUregisters_[fpureg]) = value;
+  *bit_cast<float*>(&FPUregisters_[fpureg]) = value;
 }
 
 
 void Simulator::set_fpu_register_double(int fpureg, double value) {
   DCHECK((fpureg >= 0) && (fpureg < kNumFPURegisters));
-  *BitCast<double*>(&FPUregisters_[fpureg]) = value;
+  *bit_cast<double*>(&FPUregisters_[fpureg]) = value;
 }
 
 
@@ -1109,22 +1109,21 @@ int32_t Simulator::get_fpu_register_signed_word(int fpureg) const {
 }
 
 
-uint32_t Simulator::get_fpu_register_hi_word(int fpureg) const {
+int32_t Simulator::get_fpu_register_hi_word(int fpureg) const {
   DCHECK((fpureg >= 0) && (fpureg < kNumFPURegisters));
-  return static_cast<uint32_t>((FPUregisters_[fpureg] >> 32) & 0xffffffff);
+  return static_cast<int32_t>((FPUregisters_[fpureg] >> 32) & 0xffffffff);
 }
 
 
 float Simulator::get_fpu_register_float(int fpureg) const {
   DCHECK((fpureg >= 0) && (fpureg < kNumFPURegisters));
-  return *BitCast<float*>(
-      const_cast<int64_t*>(&FPUregisters_[fpureg]));
+  return *bit_cast<float*>(const_cast<int64_t*>(&FPUregisters_[fpureg]));
 }
 
 
 double Simulator::get_fpu_register_double(int fpureg) const {
   DCHECK((fpureg >= 0) && (fpureg < kNumFPURegisters));
-  return *BitCast<double*>(&FPUregisters_[fpureg]);
+  return *bit_cast<double*>(&FPUregisters_[fpureg]);
 }
 
 
@@ -2074,10 +2073,8 @@ void Simulator::ConfigureTypeRegister(Instruction* instr,
           } else {
             // MIPS spec: If no bits were set in GPR rs, the result written to
             // GPR rd is 32.
-            // GCC __builtin_clz: If input is 0, the result is undefined.
             DCHECK(instr->SaValue() == 1);
-            *alu_out =
-                rs_u == 0 ? 32 : CompilerIntrinsics::CountLeadingZeros(rs_u);
+            *alu_out = base::bits::CountLeadingZeros32(rs_u);
           }
           break;
         case MFLO:
@@ -2220,9 +2217,7 @@ void Simulator::ConfigureTypeRegister(Instruction* instr,
         case CLZ:
           // MIPS32 spec: If no bits were set in GPR rs, the result written to
           // GPR rd is 32.
-          // GCC __builtin_clz: If input is 0, the result is undefined.
-          *alu_out =
-              rs_u == 0 ? 32 : CompilerIntrinsics::CountLeadingZeros(rs_u);
+          *alu_out = base::bits::CountLeadingZeros32(rs_u);
           break;
         default:
           UNREACHABLE();