} \
}
-/* cache control at backend */
-static unsigned int g_enable_cache_ctrl = 0;
-
struct dma_buf_info {
unsigned long size;
unsigned int fence_supported;
TBM_FORMAT_YUV420
};
+#ifdef ENABLE_CACHECTRL
#ifdef TGL_GET_VERSION
static inline int
_tgl_get_version(int fd)
return 1;
}
+#endif
static int
_bo_init_cache_state(tbm_bufmgr_exynos bufmgr_exynos, tbm_bo_exynos bo_exynos, int import)
{
- /* check whether cache control do or not */
- if (!g_enable_cache_ctrl)
- return 1;
-
+#ifdef ENABLE_CACHECTRL
EXYNOS_RETURN_VAL_IF_FAIL(bufmgr_exynos != NULL, 0);
EXYNOS_RETURN_VAL_IF_FAIL(bo_exynos != NULL, 0);
_tgl_set_data(bufmgr_exynos->tgl_fd, bo_exynos->name, cache_state.val);
}
+#endif
return 1;
}
static int
_bo_set_cache_state(tbm_bufmgr_exynos bufmgr_exynos, tbm_bo_exynos bo_exynos, int device, int opt)
{
- /* check whether cache control do or not */
- if (!g_enable_cache_ctrl)
- return 1;
-
+#ifdef ENABLE_CACHECTRL
EXYNOS_RETURN_VAL_IF_FAIL(bufmgr_exynos != NULL, 0);
EXYNOS_RETURN_VAL_IF_FAIL(bo_exynos != NULL, 0);
need_flush,
cntFlush);
}
+#endif
return 1;
}
static int
_bo_save_cache_state(tbm_bufmgr_exynos bufmgr_exynos, tbm_bo_exynos bo_exynos)
{
- /* check whether cache control do or not */
- if (!g_enable_cache_ctrl)
- return 1;
-
+#ifdef ENABLE_CACHECTRL
EXYNOS_RETURN_VAL_IF_FAIL(bufmgr_exynos != NULL, 0);
EXYNOS_RETURN_VAL_IF_FAIL(bo_exynos != NULL, 0);
bo_exynos->cache_state.data.cntFlush = cntFlush;
_tgl_set_data(bufmgr_exynos->tgl_fd, bo_exynos->name,
bo_exynos->cache_state.val);
+#endif
return 1;
}
static void
_bo_destroy_cache_state(tbm_bufmgr_exynos bufmgr_exynos, tbm_bo_exynos bo_exynos)
{
- /* check whether cache control do or not */
- if (!g_enable_cache_ctrl)
- return;
-
+#ifdef ENABLE_CACHECTRL
EXYNOS_RETURN_IF_FAIL(bufmgr_exynos != NULL);
EXYNOS_RETURN_IF_FAIL(bo_exynos != NULL);
return ;
_tgl_destroy(bufmgr_exynos->tgl_fd, bo_exynos->name);
+#endif
}
static int
_bufmgr_init_cache_state(tbm_bufmgr_exynos bufmgr_exynos)
{
- /* check whether cache control do or not */
- if (!g_enable_cache_ctrl)
- return 1;
-
+#ifdef ENABLE_CACHECTRL
EXYNOS_RETURN_VAL_IF_FAIL(bufmgr_exynos != NULL, 0);
if (bufmgr_exynos->use_dma_fence)
close(bufmgr_exynos->tgl_fd);
return 0;
}
+#endif
return 1;
}
static void
_bufmgr_deinit_cache_state(tbm_bufmgr_exynos bufmgr_exynos)
{
- /* check whether cache control do or not */
- if (!g_enable_cache_ctrl)
- return;
-
+#ifdef ENABLE_CACHECTRL
EXYNOS_RETURN_IF_FAIL(bufmgr_exynos != NULL);
if (bufmgr_exynos->use_dma_fence)
if (bufmgr_exynos->tgl_fd >= 0)
close(bufmgr_exynos->tgl_fd);
+#endif
}
static int
if (bo_exynos->map_cnt == 0)
_bo_save_cache_state(bufmgr_exynos, bo_exynos);
- /* check whether cache control do or not */
- if (g_enable_cache_ctrl && bo_exynos->last_map_device == TBM_DEVICE_CPU)
+#ifdef ENABLE_CACHECTRL
+ if (bo_exynos->last_map_device == TBM_DEVICE_CPU)
_exynos_cache_flush(bufmgr_exynos, bo_exynos, TBM_EXYNOS_CACHE_FLUSH_ALL);
+#endif
bo_exynos->last_map_device = -1;
if (!strncmp(value, "TW1", 4)) {
g_tbm_surface_alignment_plane = 8;
g_tbm_surface_alignment_pitch_rgb = 8;
- g_enable_cache_ctrl = 1;
} else {
g_tbm_surface_alignment_plane = 64;
g_tbm_surface_alignment_pitch_rgb = 64;