#define MFC_SOFTWARE_HASWELL 0
+#define SURFACE_STATE_PADDED_SIZE MAX(SURFACE_STATE_PADDED_SIZE_GEN6, SURFACE_STATE_PADDED_SIZE_GEN7)
+#define SURFACE_STATE_OFFSET(index) (SURFACE_STATE_PADDED_SIZE * index)
+#define BINDING_TABLE_OFFSET(index) (SURFACE_STATE_OFFSET(MAX_MEDIA_SURFACES_GEN6) + sizeof(unsigned int) * index)
+
#define B0_STEP_REV 2
#define IS_STEPPING_BPLUS(i965) ((i965->intel.revision) >= B0_STEP_REV)
OUT_BCS_BATCH(batch, MFX_AVC_IMG_STATE | (16 - 2));
/*DW1. MB setting of frame */
OUT_BCS_BATCH(batch,
- ((width_in_mbs * height_in_mbs) & 0xFFFF));
+ ((width_in_mbs * height_in_mbs - 1) & 0xFFFF));
OUT_BCS_BATCH(batch,
((height_in_mbs - 1) << 16) |
((width_in_mbs - 1) << 0));
OUT_BCS_BATCH(slice_batch, 0);
OUT_BCS_BATCH(slice_batch, MI_BATCH_BUFFER_END);
ADVANCE_BCS_BATCH(slice_batch);
+ mfc_context->aux_batchbuffer = NULL;
+ intel_batchbuffer_free(slice_batch);
}
intel_batchbuffer_end_atomic(batch);
intel_batchbuffer_flush(batch);
{
struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
- gen75_mfc_build_avc_batchbuffer(ctx, encode_state, encoder_context);
dri_bo_reference(mfc_context->aux_batchbuffer_surface.bo);
+ gen75_mfc_build_avc_batchbuffer(ctx, encode_state, encoder_context);
return mfc_context->aux_batchbuffer_surface.bo;
}
/* reconstructed surface */
obj_surface = encode_state->reconstructed_object;
- i965_check_alloc_surface_bo(ctx, obj_surface, 1, VA_FOURCC('N','V','1','2'), SUBSAMPLE_YUV420);
+ i965_check_alloc_surface_bo(ctx, obj_surface, 1, VA_FOURCC_NV12, SUBSAMPLE_YUV420);
mfc_context->pre_deblocking_output.bo = obj_surface->bo;
dri_bo_reference(mfc_context->pre_deblocking_output.bo);
mfc_context->surface_state.width = obj_surface->orig_width;