#ifndef R600_PIPE_H
#define R600_PIPE_H
-#include "../../winsys/radeon/drm/radeon_winsys.h"
-
-#include "pipe/p_state.h"
-#include "pipe/p_screen.h"
-#include "pipe/p_context.h"
-#include "util/u_math.h"
#include "util/u_slab.h"
-#include "util/u_vbuf.h"
#include "r600.h"
-#include "r600_public.h"
#include "r600_shader.h"
#include "r600_resource.h"
struct list_head head;
};
+/* This is an atom containing GPU commands that never change.
+ * This is supposed to be copied directly into the CS. */
+struct r600_command_buffer {
+ struct r600_atom atom;
+ uint32_t *buf;
+ unsigned max_num_dw;
+};
+
+struct r600_surface_sync_cmd {
+ struct r600_atom atom;
+ unsigned flush_flags; /* CP_COHER_CNTL */
+};
+
+struct r600_db_misc_state {
+ struct r600_atom atom;
+ bool occlusion_query_enabled;
+ bool flush_depthstencil_enabled;
+};
+
enum r600_pipe_state_id {
R600_PIPE_STATE_BLEND = 0,
R600_PIPE_STATE_BLEND_COLOR,
struct r600_pipe_fences fences;
unsigned num_contexts;
+ bool use_surface_alloc;
+ int glsl_feature_level;
/* for thread-safe write accessing to num_contexts */
pipe_mutex mutex_num_contexts;
unsigned sprite_coord_enable;
unsigned clip_plane_enable;
unsigned pa_sc_line_stipple;
- unsigned pa_su_sc_mode_cntl;
unsigned pa_cl_clip_cntl;
float offset_units;
float offset_scale;
+ bool scissor_enable;
};
struct r600_pipe_blend {
struct r600_pipe_state rstate;
unsigned cb_target_mask;
unsigned cb_color_control;
+ bool dual_src_blend;
};
struct r600_pipe_dsa {
struct r600_pipe_state rstate;
unsigned alpha_ref;
- unsigned db_render_override;
- unsigned db_render_control;
ubyte valuemask[2];
ubyte writemask[2];
+ bool is_flush;
};
struct r600_vertex_element
{
unsigned count;
struct pipe_vertex_element elements[PIPE_MAX_ATTRIBS];
- struct u_vbuf_elements *vmgr_elements;
struct r600_resource *fetch_shader;
unsigned fs_size;
struct r600_pipe_state rstate;
- /* if offset is to big for fetch instructio we need to alterate
- * offset of vertex buffer, record here the offset need to add
- */
- unsigned vbuffer_need_offset;
- unsigned vbuffer_offset[PIPE_MAX_ATTRIBS];
};
struct r600_pipe_shader {
unsigned sprite_coord_enable;
unsigned flatshade;
unsigned pa_cl_vs_out_cntl;
+ unsigned ps_cb_shader_mask;
struct pipe_stream_output_info so;
};
struct r600_fence {
struct pipe_reference reference;
unsigned index; /* in the shared bo */
+ struct r600_resource *sleep_bo;
struct list_head head;
};
ubyte writemask[2];
};
+struct r600_constant_buffer
+{
+ struct pipe_resource *buffer;
+ unsigned buffer_offset;
+ unsigned buffer_size;
+};
+
+struct r600_constbuf_state
+{
+ struct r600_atom atom;
+ struct r600_constant_buffer cb[PIPE_MAX_CONSTANT_BUFFERS];
+ uint32_t enabled_mask;
+ uint32_t dirty_mask;
+};
+
struct r600_context {
struct pipe_context context;
struct blitter_context *blitter;
enum radeon_family family;
enum chip_class chip_class;
+ boolean has_vertex_cache;
unsigned r6xx_num_clause_temp_gprs;
void *custom_dsa_flush;
struct r600_screen *screen;
struct radeon_winsys *ws;
struct r600_pipe_state *states[R600_PIPE_NSTATES];
struct r600_vertex_element *vertex_elements;
- struct r600_pipe_resource_state fs_resource[PIPE_MAX_ATTRIBS];
struct pipe_framebuffer_state framebuffer;
unsigned cb_target_mask;
+ unsigned fb_cb_shader_mask;
+ unsigned cb_shader_mask;
unsigned cb_color_control;
unsigned pa_sc_line_stipple;
- unsigned pa_su_sc_mode_cntl;
unsigned pa_cl_clip_cntl;
/* for saving when using blitter */
struct pipe_stencil_ref stencil_ref;
struct pipe_viewport_state viewport;
struct pipe_clip_state clip;
- struct r600_pipe_state config;
struct r600_pipe_shader *ps_shader;
struct r600_pipe_shader *vs_shader;
- struct r600_pipe_state vs_const_buffer;
- struct r600_pipe_resource_state vs_const_buffer_resource[R600_MAX_CONST_BUFFERS];
- struct r600_pipe_state ps_const_buffer;
- struct r600_pipe_resource_state ps_const_buffer_resource[R600_MAX_CONST_BUFFERS];
struct r600_pipe_rasterizer *rasterizer;
struct r600_pipe_state vgt;
struct r600_pipe_state spi;
unsigned default_ps_gprs, default_vs_gprs;
- /* States based on r600_state. */
+ /* States based on r600_atom. */
struct list_head dirty_states;
+ struct r600_command_buffer start_cs_cmd; /* invariant state mostly */
+ struct r600_surface_sync_cmd surface_sync_cmd;
+ struct r600_atom r6xx_flush_and_inv_cmd;
+ struct r600_db_misc_state db_misc_state;
+ struct r600_atom vertex_buffer_state;
+ struct r600_constbuf_state vs_constbuf_state;
+ struct r600_constbuf_state ps_constbuf_state;
- /* Below are variables from the old r600_context.
- */
struct radeon_winsys_cs *cs;
struct r600_range *range;
struct list_head enable_list;
unsigned pm4_dirty_cdwords;
unsigned ctx_pm4_ndwords;
- unsigned init_dwords;
-
- unsigned creloc;
- struct r600_resource **bo;
/* The list of active queries. Only one query of each type can be active. */
- struct list_head active_query_list;
- unsigned num_cs_dw_queries_suspend;
+ int num_occlusion_queries;
+
+ /* Manage queries in two separate groups:
+ * The timer ones and the others (streamout, occlusion).
+ *
+ * We do this because we should only suspend non-timer queries for u_blitter,
+ * and later if the non-timer queries are suspended, the context flush should
+ * only suspend and resume the timer queries. */
+ struct list_head active_timer_queries;
+ unsigned num_cs_dw_timer_queries_suspend;
+ struct list_head active_nontimer_queries;
+ unsigned num_cs_dw_nontimer_queries_suspend;
+
unsigned num_cs_dw_streamout_end;
unsigned backend_mask;
unsigned max_db; /* for OQ */
- unsigned num_dest_buffers;
unsigned flags;
boolean predicate_drawing;
struct r600_range ps_resources;
struct r600_range vs_resources;
- struct r600_range fs_resources;
- int num_ps_resources, num_vs_resources, num_fs_resources;
+ int num_ps_resources, num_vs_resources;
unsigned num_so_targets;
struct r600_so_target *so_targets[PIPE_MAX_SO_BUFFERS];
boolean streamout_start;
unsigned streamout_append_bitmask;
- unsigned *vs_so_stride_in_dw;
+
+ /* There is no scissor enable bit on r6xx, so we must use a workaround.
+ * These track the current scissor state. */
+ bool scissor_enable;
+ struct pipe_scissor_state scissor_state;
+
+ /* With rasterizer discard, there doesn't have to be a pixel shader.
+ * In that case, we bind this one: */
+ void *dummy_pixel_shader;
+
+ bool vertex_buffers_dirty;
+ boolean dual_src_blend;
+ unsigned color0_format;
+
+ struct pipe_index_buffer index_buffer;
+ struct pipe_vertex_buffer vertex_buffer[PIPE_MAX_ATTRIBS];
+ unsigned nr_vertex_buffers;
};
static INLINE void r600_emit_atom(struct r600_context *rctx, struct r600_atom *atom)
/* evergreen_state.c */
void evergreen_init_state_functions(struct r600_context *rctx);
-void evergreen_init_config(struct r600_context *rctx);
+void evergreen_init_atom_start_cs(struct r600_context *rctx);
void evergreen_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader);
void evergreen_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader);
void evergreen_fetch_shader(struct pipe_context *ctx, struct r600_vertex_element *ve);
void *evergreen_create_db_flush_dsa(struct r600_context *rctx);
void evergreen_polygon_offset_update(struct r600_context *rctx);
-void evergreen_pipe_init_buffer_resource(struct r600_context *rctx,
- struct r600_pipe_resource_state *rstate);
-void evergreen_pipe_mod_buffer_resource(struct pipe_context *ctx,
- struct r600_pipe_resource_state *rstate,
- struct r600_resource *rbuffer,
- unsigned offset, unsigned stride,
- enum radeon_bo_usage usage);
boolean evergreen_is_format_supported(struct pipe_screen *screen,
enum pipe_format format,
enum pipe_texture_target target,
struct pipe_resource *r600_user_buffer_create(struct pipe_screen *screen,
void *ptr, unsigned bytes,
unsigned bind);
-void r600_upload_index_buffer(struct r600_context *rctx,
- struct pipe_index_buffer *ib, unsigned count);
-
/* r600_pipe.c */
void r600_flush(struct pipe_context *ctx, struct pipe_fence_handle **fence,
/* r600_query.c */
void r600_init_query_functions(struct r600_context *rctx);
+void r600_suspend_nontimer_queries(struct r600_context *ctx);
+void r600_resume_nontimer_queries(struct r600_context *ctx);
+void r600_suspend_timer_queries(struct r600_context *ctx);
+void r600_resume_timer_queries(struct r600_context *ctx);
/* r600_resource.c */
void r600_init_context_resource_functions(struct r600_context *r600);
struct r600_shader *ps, int id);
/* r600_state.c */
+void r600_set_scissor_state(struct r600_context *rctx,
+ const struct pipe_scissor_state *state);
void r600_update_sampler_states(struct r600_context *rctx);
void r600_init_state_functions(struct r600_context *rctx);
-void r600_init_config(struct r600_context *rctx);
+void r600_init_atom_start_cs(struct r600_context *rctx);
void r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader);
void r600_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader);
void r600_fetch_shader(struct pipe_context *ctx, struct r600_vertex_element *ve);
void *r600_create_db_flush_dsa(struct r600_context *rctx);
void r600_polygon_offset_update(struct r600_context *rctx);
-void r600_pipe_init_buffer_resource(struct r600_context *rctx,
- struct r600_pipe_resource_state *rstate);
-void r600_pipe_mod_buffer_resource(struct r600_pipe_resource_state *rstate,
- struct r600_resource *rbuffer,
- unsigned offset, unsigned stride,
- enum radeon_bo_usage usage);
void r600_adjust_gprs(struct r600_context *rctx);
boolean r600_is_format_supported(struct pipe_screen *screen,
enum pipe_format format,
unsigned count);
/* r600_state_common.c */
+void r600_init_atom(struct r600_atom *atom,
+ void (*emit)(struct r600_context *ctx, struct r600_atom *state),
+ unsigned num_dw, enum r600_atom_flags flags);
+void r600_init_common_atoms(struct r600_context *rctx);
+unsigned r600_get_cb_flush_flags(struct r600_context *rctx);
+void r600_texture_barrier(struct pipe_context *ctx);
void r600_set_index_buffer(struct pipe_context *ctx,
const struct pipe_index_buffer *ib);
void r600_set_vertex_buffers(struct pipe_context *ctx, unsigned count,
const struct pipe_vertex_element *elements);
void r600_delete_vertex_element(struct pipe_context *ctx, void *state);
void r600_bind_blend_state(struct pipe_context *ctx, void *state);
+void r600_set_blend_color(struct pipe_context *ctx,
+ const struct pipe_blend_color *state);
void r600_bind_dsa_state(struct pipe_context *ctx, void *state);
+void r600_set_max_scissor(struct r600_context *rctx);
void r600_bind_rs_state(struct pipe_context *ctx, void *state);
void r600_delete_rs_state(struct pipe_context *ctx, void *state);
void r600_sampler_view_destroy(struct pipe_context *ctx,
void r600_bind_vs_shader(struct pipe_context *ctx, void *state);
void r600_delete_ps_shader(struct pipe_context *ctx, void *state);
void r600_delete_vs_shader(struct pipe_context *ctx, void *state);
+void r600_constant_buffers_dirty(struct r600_context *rctx, struct r600_constbuf_state *state);
void r600_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index,
struct pipe_resource *buffer);
struct pipe_stream_output_target *
void r600_set_pipe_stencil_ref(struct pipe_context *ctx,
const struct pipe_stencil_ref *state);
void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info);
+uint32_t r600_translate_stencil_op(int s_op);
+uint32_t r600_translate_fill(uint32_t func);
+unsigned r600_tex_wrap(unsigned wrap);
+unsigned r600_tex_filter(unsigned filter);
+unsigned r600_tex_mipfilter(unsigned filter);
+unsigned r600_tex_compare(unsigned compare);
+
+/*
+ * Helpers for building command buffers
+ */
+
+#define PKT3_SET_CONFIG_REG 0x68
+#define PKT3_SET_CONTEXT_REG 0x69
+#define PKT3_SET_CTL_CONST 0x6F
+#define PKT3_SET_LOOP_CONST 0x6C
+
+#define R600_CONFIG_REG_OFFSET 0x08000
+#define R600_CONTEXT_REG_OFFSET 0x28000
+#define R600_CTL_CONST_OFFSET 0x3CFF0
+#define R600_LOOP_CONST_OFFSET 0X0003E200
+#define EG_LOOP_CONST_OFFSET 0x0003A200
+
+#define PKT_TYPE_S(x) (((x) & 0x3) << 30)
+#define PKT_COUNT_S(x) (((x) & 0x3FFF) << 16)
+#define PKT3_IT_OPCODE_S(x) (((x) & 0xFF) << 8)
+#define PKT3_PREDICATE(x) (((x) >> 0) & 0x1)
+#define PKT3(op, count, predicate) (PKT_TYPE_S(3) | PKT_COUNT_S(count) | PKT3_IT_OPCODE_S(op) | PKT3_PREDICATE(predicate))
+
+static INLINE void r600_store_value(struct r600_command_buffer *cb, unsigned value)
+{
+ cb->buf[cb->atom.num_dw++] = value;
+}
+
+static INLINE void r600_store_config_reg_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
+{
+ assert(reg < R600_CONTEXT_REG_OFFSET);
+ assert(cb->atom.num_dw+2+num <= cb->max_num_dw);
+ cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_CONFIG_REG, num, 0);
+ cb->buf[cb->atom.num_dw++] = (reg - R600_CONFIG_REG_OFFSET) >> 2;
+}
+
+static INLINE void r600_store_context_reg_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
+{
+ assert(reg >= R600_CONTEXT_REG_OFFSET && reg < R600_CTL_CONST_OFFSET);
+ assert(cb->atom.num_dw+2+num <= cb->max_num_dw);
+ cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_CONTEXT_REG, num, 0);
+ cb->buf[cb->atom.num_dw++] = (reg - R600_CONTEXT_REG_OFFSET) >> 2;
+}
+
+static INLINE void r600_store_ctl_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
+{
+ assert(reg >= R600_CTL_CONST_OFFSET);
+ assert(cb->atom.num_dw+2+num <= cb->max_num_dw);
+ cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_CTL_CONST, num, 0);
+ cb->buf[cb->atom.num_dw++] = (reg - R600_CTL_CONST_OFFSET) >> 2;
+}
+
+static INLINE void r600_store_loop_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
+{
+ assert(reg >= R600_LOOP_CONST_OFFSET);
+ assert(cb->atom.num_dw+2+num <= cb->max_num_dw);
+ cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_LOOP_CONST, num, 0);
+ cb->buf[cb->atom.num_dw++] = (reg - R600_LOOP_CONST_OFFSET) >> 2;
+}
+
+static INLINE void eg_store_loop_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
+{
+ assert(reg >= EG_LOOP_CONST_OFFSET);
+ assert(cb->atom.num_dw+2+num <= cb->max_num_dw);
+ cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_LOOP_CONST, num, 0);
+ cb->buf[cb->atom.num_dw++] = (reg - EG_LOOP_CONST_OFFSET) >> 2;
+}
+
+static INLINE void r600_store_config_reg(struct r600_command_buffer *cb, unsigned reg, unsigned value)
+{
+ r600_store_config_reg_seq(cb, reg, 1);
+ r600_store_value(cb, value);
+}
+
+static INLINE void r600_store_context_reg(struct r600_command_buffer *cb, unsigned reg, unsigned value)
+{
+ r600_store_context_reg_seq(cb, reg, 1);
+ r600_store_value(cb, value);
+}
+
+static INLINE void r600_store_ctl_const(struct r600_command_buffer *cb, unsigned reg, unsigned value)
+{
+ r600_store_ctl_const_seq(cb, reg, 1);
+ r600_store_value(cb, value);
+}
+
+static INLINE void r600_store_loop_const(struct r600_command_buffer *cb, unsigned reg, unsigned value)
+{
+ r600_store_loop_const_seq(cb, reg, 1);
+ r600_store_value(cb, value);
+}
+
+static INLINE void eg_store_loop_const(struct r600_command_buffer *cb, unsigned reg, unsigned value)
+{
+ eg_store_loop_const_seq(cb, reg, 1);
+ r600_store_value(cb, value);
+}
+
+void r600_init_command_buffer(struct r600_command_buffer *cb, unsigned num_dw, enum r600_atom_flags flags);
+void r600_release_command_buffer(struct r600_command_buffer *cb);
+
+/*
+ * Helpers for emitting state into a command stream directly.
+ */
+
+static INLINE unsigned r600_context_bo_reloc(struct r600_context *ctx, struct r600_resource *rbo,
+ enum radeon_bo_usage usage)
+{
+ assert(usage);
+ return ctx->ws->cs_add_reloc(ctx->cs, rbo->cs_buf, usage, rbo->domains) * 4;
+}
+
+static INLINE void r600_write_value(struct radeon_winsys_cs *cs, unsigned value)
+{
+ cs->buf[cs->cdw++] = value;
+}
+
+static INLINE void r600_write_config_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
+{
+ assert(reg < R600_CONTEXT_REG_OFFSET);
+ assert(cs->cdw+2+num <= RADEON_MAX_CMDBUF_DWORDS);
+ cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONFIG_REG, num, 0);
+ cs->buf[cs->cdw++] = (reg - R600_CONFIG_REG_OFFSET) >> 2;
+}
+
+static INLINE void r600_write_context_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
+{
+ assert(reg >= R600_CONTEXT_REG_OFFSET && reg < R600_CTL_CONST_OFFSET);
+ assert(cs->cdw+2+num <= RADEON_MAX_CMDBUF_DWORDS);
+ cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONTEXT_REG, num, 0);
+ cs->buf[cs->cdw++] = (reg - R600_CONTEXT_REG_OFFSET) >> 2;
+}
+
+static INLINE void r600_write_ctl_const_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
+{
+ assert(reg >= R600_CTL_CONST_OFFSET);
+ assert(cs->cdw+2+num <= RADEON_MAX_CMDBUF_DWORDS);
+ cs->buf[cs->cdw++] = PKT3(PKT3_SET_CTL_CONST, num, 0);
+ cs->buf[cs->cdw++] = (reg - R600_CTL_CONST_OFFSET) >> 2;
+}
+
+static INLINE void r600_write_config_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
+{
+ r600_write_config_reg_seq(cs, reg, 1);
+ r600_write_value(cs, value);
+}
+
+static INLINE void r600_write_context_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
+{
+ r600_write_context_reg_seq(cs, reg, 1);
+ r600_write_value(cs, value);
+}
+
+static INLINE void r600_write_ctl_const(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
+{
+ r600_write_ctl_const_seq(cs, reg, 1);
+ r600_write_value(cs, value);
+}
/*
* common helpers
x >= 4096 ? 0xffff : x * 16;
}
+static INLINE uint64_t r600_resource_va(struct pipe_screen *screen, struct pipe_resource *resource)
+{
+ struct r600_screen *rscreen = (struct r600_screen*)screen;
+ struct r600_resource *rresource = (struct r600_resource*)resource;
+
+ return rscreen->ws->buffer_get_virtual_address(rresource->cs_buf);
+}
+
#endif
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