#ifndef R600_PIPE_H
#define R600_PIPE_H
-#include "../../winsys/radeon/drm/radeon_winsys.h"
-
-#include "pipe/p_state.h"
-#include "pipe/p_screen.h"
-#include "pipe/p_context.h"
-#include "util/u_math.h"
#include "util/u_slab.h"
-#include "util/u_vbuf.h"
#include "r600.h"
-#include "r600_public.h"
#include "r600_shader.h"
#include "r600_resource.h"
unsigned max_num_dw;
};
-struct r600_atom_surface_sync {
+struct r600_surface_sync_cmd {
struct r600_atom atom;
unsigned flush_flags; /* CP_COHER_CNTL */
};
-struct r600_atom_db_misc_state {
+struct r600_db_misc_state {
struct r600_atom atom;
bool occlusion_query_enabled;
bool flush_depthstencil_enabled;
};
-struct r600_atom_eg_strmout_config {
- struct r600_atom atom;
- bool rasterizer_discard;
- bool stream0_enable;
-};
-
enum r600_pipe_state_id {
R600_PIPE_STATE_BLEND = 0,
R600_PIPE_STATE_BLEND_COLOR,
unsigned num_contexts;
bool use_surface_alloc;
+ int glsl_feature_level;
/* for thread-safe write accessing to num_contexts */
pipe_mutex mutex_num_contexts;
float offset_units;
float offset_scale;
bool scissor_enable;
- bool rasterizer_discard;
};
struct r600_pipe_blend {
struct r600_pipe_state rstate;
unsigned cb_target_mask;
unsigned cb_color_control;
+ bool dual_src_blend;
};
struct r600_pipe_dsa {
{
unsigned count;
struct pipe_vertex_element elements[PIPE_MAX_ATTRIBS];
- struct u_vbuf_elements *vmgr_elements;
struct r600_resource *fetch_shader;
unsigned fs_size;
struct r600_pipe_state rstate;
- /* if offset is to big for fetch instructio we need to alterate
- * offset of vertex buffer, record here the offset need to add
- */
- unsigned vbuffer_need_offset;
- unsigned vbuffer_offset[PIPE_MAX_ATTRIBS];
};
struct r600_pipe_shader {
unsigned sprite_coord_enable;
unsigned flatshade;
unsigned pa_cl_vs_out_cntl;
+ unsigned ps_cb_shader_mask;
struct pipe_stream_output_info so;
};
ubyte writemask[2];
};
+struct r600_constant_buffer
+{
+ struct pipe_resource *buffer;
+ unsigned buffer_offset;
+ unsigned buffer_size;
+};
+
+struct r600_constbuf_state
+{
+ struct r600_atom atom;
+ struct r600_constant_buffer cb[PIPE_MAX_CONSTANT_BUFFERS];
+ uint32_t enabled_mask;
+ uint32_t dirty_mask;
+};
+
struct r600_context {
struct pipe_context context;
struct blitter_context *blitter;
enum radeon_family family;
enum chip_class chip_class;
+ boolean has_vertex_cache;
unsigned r6xx_num_clause_temp_gprs;
void *custom_dsa_flush;
struct r600_screen *screen;
struct radeon_winsys *ws;
struct r600_pipe_state *states[R600_PIPE_NSTATES];
struct r600_vertex_element *vertex_elements;
- struct r600_pipe_resource_state fs_resource[PIPE_MAX_ATTRIBS];
struct pipe_framebuffer_state framebuffer;
unsigned cb_target_mask;
+ unsigned fb_cb_shader_mask;
+ unsigned cb_shader_mask;
unsigned cb_color_control;
unsigned pa_sc_line_stipple;
unsigned pa_cl_clip_cntl;
struct pipe_clip_state clip;
struct r600_pipe_shader *ps_shader;
struct r600_pipe_shader *vs_shader;
- struct r600_pipe_state vs_const_buffer;
- struct r600_pipe_resource_state vs_const_buffer_resource[R600_MAX_CONST_BUFFERS];
- struct r600_pipe_state ps_const_buffer;
- struct r600_pipe_resource_state ps_const_buffer_resource[R600_MAX_CONST_BUFFERS];
struct r600_pipe_rasterizer *rasterizer;
struct r600_pipe_state vgt;
struct r600_pipe_state spi;
unsigned default_ps_gprs, default_vs_gprs;
- /* States based on r600_state. */
+ /* States based on r600_atom. */
struct list_head dirty_states;
- struct r600_command_buffer atom_start_cs; /* invariant state mostly */
- struct r600_atom_surface_sync atom_surface_sync;
- struct r600_atom atom_r6xx_flush_and_inv;
- struct r600_atom_db_misc_state atom_db_misc_state;
- struct r600_atom_eg_strmout_config atom_eg_strmout_config;
-
- /* Below are variables from the old r600_context.
- */
+ struct r600_command_buffer start_cs_cmd; /* invariant state mostly */
+ struct r600_surface_sync_cmd surface_sync_cmd;
+ struct r600_atom r6xx_flush_and_inv_cmd;
+ struct r600_db_misc_state db_misc_state;
+ struct r600_atom vertex_buffer_state;
+ struct r600_constbuf_state vs_constbuf_state;
+ struct r600_constbuf_state ps_constbuf_state;
+
struct radeon_winsys_cs *cs;
struct r600_range *range;
boolean predicate_drawing;
struct r600_range ps_resources;
struct r600_range vs_resources;
- struct r600_range fs_resources;
- int num_ps_resources, num_vs_resources, num_fs_resources;
+ int num_ps_resources, num_vs_resources;
unsigned num_so_targets;
struct r600_so_target *so_targets[PIPE_MAX_SO_BUFFERS];
/* With rasterizer discard, there doesn't have to be a pixel shader.
* In that case, we bind this one: */
void *dummy_pixel_shader;
+
+ bool vertex_buffers_dirty;
+ boolean dual_src_blend;
+ unsigned color0_format;
+
+ struct pipe_index_buffer index_buffer;
+ struct pipe_vertex_buffer vertex_buffer[PIPE_MAX_ATTRIBS];
+ unsigned nr_vertex_buffers;
};
static INLINE void r600_emit_atom(struct r600_context *rctx, struct r600_atom *atom)
void evergreen_fetch_shader(struct pipe_context *ctx, struct r600_vertex_element *ve);
void *evergreen_create_db_flush_dsa(struct r600_context *rctx);
void evergreen_polygon_offset_update(struct r600_context *rctx);
-void evergreen_pipe_init_buffer_resource(struct r600_context *rctx,
- struct r600_pipe_resource_state *rstate);
-void evergreen_pipe_mod_buffer_resource(struct pipe_context *ctx,
- struct r600_pipe_resource_state *rstate,
- struct r600_resource *rbuffer,
- unsigned offset, unsigned stride,
- enum radeon_bo_usage usage);
boolean evergreen_is_format_supported(struct pipe_screen *screen,
enum pipe_format format,
enum pipe_texture_target target,
unsigned sample_count,
unsigned usage);
-void evergreen_set_rasterizer_discard(struct pipe_context *ctx, boolean discard);
/* r600_blit.c */
void r600_init_blit_functions(struct r600_context *rctx);
struct pipe_resource *r600_user_buffer_create(struct pipe_screen *screen,
void *ptr, unsigned bytes,
unsigned bind);
-void r600_upload_index_buffer(struct r600_context *rctx,
- struct pipe_index_buffer *ib, unsigned count);
-
/* r600_pipe.c */
void r600_flush(struct pipe_context *ctx, struct pipe_fence_handle **fence,
void r600_fetch_shader(struct pipe_context *ctx, struct r600_vertex_element *ve);
void *r600_create_db_flush_dsa(struct r600_context *rctx);
void r600_polygon_offset_update(struct r600_context *rctx);
-void r600_pipe_init_buffer_resource(struct r600_context *rctx,
- struct r600_pipe_resource_state *rstate);
-void r600_pipe_mod_buffer_resource(struct r600_pipe_resource_state *rstate,
- struct r600_resource *rbuffer,
- unsigned offset, unsigned stride,
- enum radeon_bo_usage usage);
void r600_adjust_gprs(struct r600_context *rctx);
boolean r600_is_format_supported(struct pipe_screen *screen,
enum pipe_format format,
void r600_bind_vs_shader(struct pipe_context *ctx, void *state);
void r600_delete_ps_shader(struct pipe_context *ctx, void *state);
void r600_delete_vs_shader(struct pipe_context *ctx, void *state);
+void r600_constant_buffers_dirty(struct r600_context *rctx, struct r600_constbuf_state *state);
void r600_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index,
struct pipe_resource *buffer);
struct pipe_stream_output_target *
* Helpers for emitting state into a command stream directly.
*/
+static INLINE unsigned r600_context_bo_reloc(struct r600_context *ctx, struct r600_resource *rbo,
+ enum radeon_bo_usage usage)
+{
+ assert(usage);
+ return ctx->ws->cs_add_reloc(ctx->cs, rbo->cs_buf, usage, rbo->domains) * 4;
+}
+
static INLINE void r600_write_value(struct radeon_winsys_cs *cs, unsigned value)
{
cs->buf[cs->cdw++] = value;
x >= 4096 ? 0xffff : x * 16;
}
+static INLINE uint64_t r600_resource_va(struct pipe_screen *screen, struct pipe_resource *resource)
+{
+ struct r600_screen *rscreen = (struct r600_screen*)screen;
+ struct r600_resource *rresource = (struct r600_resource*)resource;
+
+ return rscreen->ws->buffer_get_virtual_address(rresource->cs_buf);
+}
+
#endif
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