#ifndef R600_PIPE_H
#define R600_PIPE_H
+#include "util/u_blitter.h"
#include "util/u_slab.h"
#include "r600.h"
#include "r600_llvm.h"
struct r600_db_misc_state {
struct r600_atom atom;
bool occlusion_query_enabled;
- bool flush_depthstencil_enabled;
+ bool flush_depthstencil_through_cb;
+ bool copy_depth, copy_stencil;
+ unsigned copy_sample;
+ unsigned log_samples;
+};
+
+struct r600_cb_misc_state {
+ struct r600_atom atom;
+ unsigned cb_color_control; /* this comes from blend state */
+ unsigned blend_colormask; /* 8*4 bits for 8 RGBA colorbuffers */
+ unsigned nr_cbufs;
+ unsigned nr_ps_color_outputs;
+ bool multiwrite;
+ bool dual_src_blend;
+};
+
+struct r600_alphatest_state {
+ struct r600_atom atom;
+ unsigned sx_alpha_test_control; /* this comes from dsa state */
+ unsigned sx_alpha_ref; /* this comes from dsa state */
+ bool bypass;
+ bool cb0_export_16bpc; /* from set_framebuffer_state */
+};
+
+struct r600_cs_shader_state {
+ struct r600_atom atom;
+ struct r600_pipe_compute *shader;
+};
+
+struct r600_sample_mask {
+ struct r600_atom atom;
+ uint16_t sample_mask; /* there are only 8 bits on EG, 16 bits on Cayman */
};
enum r600_pipe_state_id {
struct compute_memory_pool;
void compute_memory_pool_delete(struct compute_memory_pool* pool);
struct compute_memory_pool* compute_memory_pool_new(
- int64_t initial_size_in_dw,
struct r600_screen *rscreen);
struct r600_pipe_fences {
struct r600_tiling_info tiling_info;
struct r600_pipe_fences fences;
- bool use_surface_alloc;
- int glsl_feature_level;
-
/*for compute global memory binding, we allocate stuff here, instead of
* buffers.
* XXX: Not sure if this is the best place for global_pool. Also,
struct r600_pipe_sampler_view {
struct pipe_sampler_view base;
- struct r600_pipe_resource_state state;
+ struct r600_resource *tex_resource;
+ uint32_t tex_resource_words[8];
};
struct r600_pipe_rasterizer {
float offset_units;
float offset_scale;
bool scissor_enable;
+ bool multisample_enable;
};
struct r600_pipe_blend {
unsigned cb_target_mask;
unsigned cb_color_control;
bool dual_src_blend;
+ bool alpha_to_one;
};
struct r600_pipe_dsa {
unsigned alpha_ref;
ubyte valuemask[2];
ubyte writemask[2];
- bool is_flush;
unsigned sx_alpha_test_control;
};
unsigned sprite_coord_enable;
unsigned flatshade;
unsigned pa_cl_vs_out_cntl;
- unsigned ps_cb_shader_mask;
+ unsigned nr_ps_color_outputs;
unsigned key;
unsigned db_shader_control;
unsigned ps_depth_export;
};
struct r600_pipe_sampler_state {
- struct r600_pipe_state rstate;
- boolean seamless_cube_map;
+ uint32_t tex_sampler_words[3];
+ uint32_t border_color[4];
+ bool border_color_use;
+ bool seamless_cube_map;
};
/* needed for blitter save */
#define NUM_TEX_UNITS 16
-struct r600_textures_info {
+struct r600_seamless_cube_map {
+ struct r600_atom atom;
+ bool enabled;
+};
+
+struct r600_samplerview_state {
+ struct r600_atom atom;
struct r600_pipe_sampler_view *views[NUM_TEX_UNITS];
+ uint32_t enabled_mask;
+ uint32_t dirty_mask;
+ uint32_t compressed_depthtex_mask; /* which textures are depth */
+ uint32_t compressed_colortex_mask;
+};
+
+struct r600_textures_info {
+ struct r600_samplerview_state views;
+ struct r600_atom atom_sampler;
struct r600_pipe_sampler_state *samplers[NUM_TEX_UNITS];
- unsigned n_views;
unsigned n_samplers;
- bool samplers_dirty;
bool is_array_sampler[NUM_TEX_UNITS];
};
struct r600_fence {
struct pipe_reference reference;
unsigned index; /* in the shared bo */
- struct r600_resource *sleep_bo;
+ struct r600_resource *sleep_bo;
struct list_head head;
};
uint32_t dirty_mask;
};
+struct r600_vertexbuf_state
+{
+ struct r600_atom atom;
+ struct pipe_vertex_buffer vb[PIPE_MAX_ATTRIBS];
+ uint32_t enabled_mask; /* non-NULL buffers */
+ uint32_t dirty_mask;
+};
+
struct r600_context {
struct pipe_context context;
struct blitter_context *blitter;
boolean has_vertex_cache;
unsigned r6xx_num_clause_temp_gprs;
void *custom_dsa_flush;
+ void *custom_blend_resolve;
+ void *custom_blend_decompress;
+
struct r600_screen *screen;
struct radeon_winsys *ws;
struct r600_pipe_state *states[R600_PIPE_NSTATES];
struct r600_vertex_element *vertex_elements;
struct pipe_framebuffer_state framebuffer;
- unsigned cb_target_mask;
- unsigned fb_cb_shader_mask;
- unsigned sx_alpha_test_control;
- unsigned cb_shader_mask;
+ unsigned compressed_cb_mask;
+ unsigned compute_cb_target_mask;
unsigned db_shader_control;
- unsigned cb_color_control;
unsigned pa_sc_line_stipple;
unsigned pa_cl_clip_cntl;
/* for saving when using blitter */
struct pipe_clip_state clip;
struct r600_pipe_shader_selector *ps_shader;
struct r600_pipe_shader_selector *vs_shader;
- struct r600_pipe_compute *cs_shader;
struct r600_pipe_rasterizer *rasterizer;
struct r600_pipe_state vgt;
struct r600_pipe_state spi;
unsigned sprite_coord_enable;
boolean flatshade;
boolean export_16bpc;
- unsigned alpha_ref;
- boolean alpha_ref_dirty;
unsigned nr_cbufs;
- struct r600_textures_info vs_samplers;
- struct r600_textures_info ps_samplers;
+ bool alpha_to_one;
+ bool multisample_enable;
+ bool cb0_is_integer;
struct u_upload_mgr *uploader;
struct util_slab_mempool pool_transfers;
- boolean have_depth_texture, have_depth_fb;
unsigned default_ps_gprs, default_vs_gprs;
+ /* current unaccounted memory usage */
+ uint64_t vram;
+ uint64_t gtt;
+
/* States based on r600_atom. */
struct list_head dirty_states;
struct r600_command_buffer start_cs_cmd; /* invariant state mostly */
struct r600_command_buffer start_compute_cs_cmd;
struct r600_surface_sync_cmd surface_sync_cmd;
struct r600_atom r6xx_flush_and_inv_cmd;
+ struct r600_alphatest_state alphatest_state;
+ struct r600_cb_misc_state cb_misc_state;
struct r600_db_misc_state db_misc_state;
- struct r600_atom vertex_buffer_state;
+ /** Vertex buffers for fetch shaders */
+ struct r600_vertexbuf_state vertex_buffer_state;
+ /** Vertex buffers for compute shaders */
+ struct r600_vertexbuf_state cs_vertex_buffer_state;
struct r600_constbuf_state vs_constbuf_state;
struct r600_constbuf_state ps_constbuf_state;
+ struct r600_textures_info vs_samplers;
+ struct r600_textures_info ps_samplers;
+ struct r600_seamless_cube_map seamless_cube_map;
+ struct r600_cs_shader_state cs_shader_state;
+ struct r600_sample_mask sample_mask;
+
+ /* current external blend state (from state tracker) */
+ struct r600_pipe_blend *blend;
+ /* state with disabled blending - used internally with blend_override */
+ struct r600_pipe_blend *no_blend;
+
+ /* 1 - override current blend state with no_blend, 0 - use external state */
+ unsigned blend_override;
struct radeon_winsys_cs *cs;
unsigned nblocks;
struct r600_block **blocks;
struct list_head dirty;
- struct list_head resource_dirty;
struct list_head enable_list;
unsigned pm4_dirty_cdwords;
unsigned ctx_pm4_ndwords;
unsigned max_db; /* for OQ */
unsigned flags;
boolean predicate_drawing;
- struct r600_range ps_resources;
- struct r600_range vs_resources;
- int num_ps_resources, num_vs_resources;
unsigned num_so_targets;
struct r600_so_target *so_targets[PIPE_MAX_SO_BUFFERS];
boolean dual_src_blend;
- /* Vertex and index buffers. */
- bool vertex_buffers_dirty;
+ /* Index buffer. */
struct pipe_index_buffer index_buffer;
- struct pipe_vertex_buffer vertex_buffer[PIPE_MAX_ATTRIBS];
- unsigned nr_vertex_buffers;
+
+ /* Dummy CMASK and FMASK buffers used to get around the R6xx hardware
+ * bug where valid CMASK and FMASK are required to be present to avoid
+ * a hardlock in certain operations but aren't actually used
+ * for anything useful. */
+ struct r600_resource *dummy_fmask;
+ struct r600_resource *dummy_cmask;
};
static INLINE void r600_emit_atom(struct r600_context *rctx, struct r600_atom *atom)
}
/* evergreen_state.c */
+void evergreen_init_common_regs(struct r600_command_buffer *cb,
+ enum chip_class ctx_chip_class,
+ enum radeon_family ctx_family,
+ int ctx_drm_minor);
+
void evergreen_init_state_functions(struct r600_context *rctx);
void evergreen_init_atom_start_cs(struct r600_context *rctx);
void evergreen_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader);
void evergreen_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader);
void evergreen_fetch_shader(struct pipe_context *ctx, struct r600_vertex_element *ve);
void *evergreen_create_db_flush_dsa(struct r600_context *rctx);
+void *evergreen_create_resolve_blend(struct r600_context *rctx);
+void *evergreen_create_decompress_blend(struct r600_context *rctx);
void evergreen_polygon_offset_update(struct r600_context *rctx);
boolean evergreen_is_format_supported(struct pipe_screen *screen,
enum pipe_format format,
enum pipe_texture_target target,
unsigned sample_count,
unsigned usage);
-void evergreen_cb(struct r600_context *rctx, struct r600_pipe_state *rstate,
- const struct pipe_framebuffer_state *state, int cb);
-
-
+void evergreen_init_color_surface(struct r600_context *rctx,
+ struct r600_surface *surf);
void evergreen_update_dual_export_state(struct r600_context * rctx);
/* r600_blit.c */
+void r600_copy_buffer(struct pipe_context *ctx, struct
+ pipe_resource *dst, unsigned dstx,
+ struct pipe_resource *src, const struct pipe_box *src_box);
void r600_init_blit_functions(struct r600_context *rctx);
-void r600_blit_uncompress_depth(struct pipe_context *ctx, struct r600_resource_texture *texture);
-void r600_flush_depth_textures(struct r600_context *rctx);
+void r600_blit_decompress_depth(struct pipe_context *ctx,
+ struct r600_texture *texture,
+ struct r600_texture *staging,
+ unsigned first_level, unsigned last_level,
+ unsigned first_layer, unsigned last_layer,
+ unsigned first_sample, unsigned last_sample);
+void r600_decompress_depth_textures(struct r600_context *rctx,
+ struct r600_samplerview_state *textures);
+void r600_decompress_color_textures(struct r600_context *rctx,
+ struct r600_samplerview_state *textures);
/* r600_buffer.c */
bool r600_init_resource(struct r600_screen *rscreen,
unsigned size, unsigned alignment,
unsigned bind, unsigned usage);
struct pipe_resource *r600_buffer_create(struct pipe_screen *screen,
- const struct pipe_resource *templ);
+ const struct pipe_resource *templ,
+ unsigned alignment);
/* r600_pipe.c */
void r600_flush(struct pipe_context *ctx, struct pipe_fence_handle **fence,
/* r600_state.c */
void r600_set_scissor_state(struct r600_context *rctx,
const struct pipe_scissor_state *state);
-void r600_update_sampler_states(struct r600_context *rctx);
void r600_init_state_functions(struct r600_context *rctx);
void r600_init_atom_start_cs(struct r600_context *rctx);
void r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader);
void r600_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader);
void r600_fetch_shader(struct pipe_context *ctx, struct r600_vertex_element *ve);
void *r600_create_db_flush_dsa(struct r600_context *rctx);
+void *r600_create_resolve_blend(struct r600_context *rctx);
+void *r700_create_resolve_blend(struct r600_context *rctx);
+void *r600_create_decompress_blend(struct r600_context *rctx);
void r600_polygon_offset_update(struct r600_context *rctx);
void r600_adjust_gprs(struct r600_context *rctx);
boolean r600_is_format_supported(struct pipe_screen *screen,
uint32_t r600_translate_texformat(struct pipe_screen *screen, enum pipe_format format,
const unsigned char *swizzle_view,
uint32_t *word4_p, uint32_t *yuv_format_p);
-unsigned r600_texture_get_offset(struct r600_resource_texture *rtex,
+unsigned r600_texture_get_offset(struct r600_texture *rtex,
unsigned level, unsigned layer);
/* r600_translate.c */
void r600_texture_barrier(struct pipe_context *ctx);
void r600_set_index_buffer(struct pipe_context *ctx,
const struct pipe_index_buffer *ib);
+void r600_vertex_buffers_dirty(struct r600_context *rctx);
void r600_set_vertex_buffers(struct pipe_context *ctx, unsigned count,
- const struct pipe_vertex_buffer *buffers);
+ const struct pipe_vertex_buffer *input);
+void r600_sampler_views_dirty(struct r600_context *rctx,
+ struct r600_samplerview_state *state);
+void r600_set_sampler_views(struct pipe_context *pipe,
+ unsigned shader,
+ unsigned start,
+ unsigned count,
+ struct pipe_sampler_view **views);
+void r600_bind_vs_samplers(struct pipe_context *ctx, unsigned count, void **states);
+void r600_bind_ps_samplers(struct pipe_context *ctx, unsigned count, void **states);
void *r600_create_vertex_elements(struct pipe_context *ctx,
unsigned count,
const struct pipe_vertex_element *elements);
void r600_delete_rs_state(struct pipe_context *ctx, void *state);
void r600_sampler_view_destroy(struct pipe_context *ctx,
struct pipe_sampler_view *state);
+void r600_delete_sampler(struct pipe_context *ctx, void *state);
void r600_delete_state(struct pipe_context *ctx, void *state);
void r600_bind_vertex_elements(struct pipe_context *ctx, void *state);
void *r600_create_shader_state_ps(struct pipe_context *ctx,
unsigned num_targets,
struct pipe_stream_output_target **targets,
unsigned append_bitmask);
+void r600_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask);
void r600_set_pipe_stencil_ref(struct pipe_context *ctx,
const struct pipe_stencil_ref *state);
void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info);
+void r600_draw_rectangle(struct blitter_context *blitter,
+ unsigned x1, unsigned y1, unsigned x2, unsigned y2, float depth,
+ enum blitter_attrib_type type, const union pipe_color_union *attrib);
uint32_t r600_translate_stencil_op(int s_op);
uint32_t r600_translate_fill(uint32_t func);
unsigned r600_tex_wrap(unsigned wrap);
#define PKT3_PREDICATE(x) (((x) >> 0) & 0x1)
#define PKT3(op, count, predicate) (PKT_TYPE_S(3) | PKT_COUNT_S(count) | PKT3_IT_OPCODE_S(op) | PKT3_PREDICATE(predicate))
+#define RADEON_CP_PACKET3_COMPUTE_MODE 0x00000002
+
+/*Evergreen Compute packet3*/
+#define PKT3C(op, count, predicate) (PKT_TYPE_S(3) | PKT3_IT_OPCODE_S(op) | PKT_COUNT_S(count) | PKT3_PREDICATE(predicate) | RADEON_CP_PACKET3_COMPUTE_MODE)
+
static INLINE void r600_store_value(struct r600_command_buffer *cb, unsigned value)
{
cb->buf[cb->atom.num_dw++] = value;
cs->buf[cs->cdw++] = value;
}
+static INLINE void r600_write_array(struct radeon_winsys_cs *cs, unsigned num, unsigned *ptr)
+{
+ assert(cs->cdw+num <= RADEON_MAX_CMDBUF_DWORDS);
+ memcpy(&cs->buf[cs->cdw], ptr, num * sizeof(ptr[0]));
+ cs->cdw += num;
+}
+
static INLINE void r600_write_config_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
{
assert(reg < R600_CONTEXT_REG_OFFSET);
cs->buf[cs->cdw++] = (reg - R600_CONTEXT_REG_OFFSET) >> 2;
}
+static INLINE void r600_write_compute_context_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
+{
+ r600_write_context_reg_seq(cs, reg, num);
+ /* Set the compute bit on the packet header */
+ cs->buf[cs->cdw - 2] |= RADEON_CP_PACKET3_COMPUTE_MODE;
+}
+
static INLINE void r600_write_ctl_const_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
{
assert(reg >= R600_CTL_CONST_OFFSET);
r600_write_value(cs, value);
}
+static INLINE void r600_write_compute_context_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
+{
+ r600_write_compute_context_reg_seq(cs, reg, 1);
+ r600_write_value(cs, value);
+}
+
static INLINE void r600_write_ctl_const(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
{
r600_write_ctl_const_seq(cs, reg, 1);
return rscreen->ws->buffer_get_virtual_address(rresource->cs_buf);
}
+static INLINE void r600_context_add_resource_size(struct pipe_context *ctx, struct pipe_resource *r)
+{
+ struct r600_context *rctx = (struct r600_context *)ctx;
+ struct r600_resource *rr = (struct r600_resource *)r;
+
+ if (r == NULL) {
+ return;
+ }
+
+ /*
+ * The idea is to compute a gross estimate of memory requirement of
+ * each draw call. After each draw call, memory will be precisely
+ * accounted. So the uncertainty is only on the current draw call.
+ * In practice this gave very good estimate (+/- 10% of the target
+ * memory limit).
+ */
+ if (rr->domains & RADEON_DOMAIN_GTT) {
+ rctx->gtt += rr->buf->size;
+ }
+ if (rr->domains & RADEON_DOMAIN_VRAM) {
+ rctx->vram += rr->buf->size;
+ }
+}
+
#endif
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