#include "util/u_slab.h"
#include "r600.h"
+#include "r600_llvm.h"
+#include "r600_public.h"
#include "r600_shader.h"
#include "r600_resource.h"
+#include "evergreen_compute.h"
#define R600_MAX_CONST_BUFFERS 2
#define R600_MAX_CONST_BUFFER_SIZE 4096
struct r600_atom atom;
uint32_t *buf;
unsigned max_num_dw;
+ unsigned pkt_flags;
};
struct r600_surface_sync_cmd {
bool flush_depthstencil_enabled;
};
+struct r600_cb_misc_state {
+ struct r600_atom atom;
+ unsigned cb_color_control; /* this comes from blend state */
+ unsigned blend_colormask; /* 8*4 bits for 8 RGBA colorbuffers */
+ unsigned nr_cbufs;
+ unsigned nr_ps_color_outputs;
+ bool multiwrite;
+ bool dual_src_blend;
+};
+
enum r600_pipe_state_id {
R600_PIPE_STATE_BLEND = 0,
R600_PIPE_STATE_BLEND_COLOR,
R600_PIPE_STATE_RESOURCE,
R600_PIPE_STATE_POLYGON_OFFSET,
R600_PIPE_STATE_FETCH_SHADER,
+ R600_PIPE_STATE_SPI,
R600_PIPE_NSTATES
};
+struct compute_memory_pool;
+void compute_memory_pool_delete(struct compute_memory_pool* pool);
+struct compute_memory_pool* compute_memory_pool_new(
+ struct r600_screen *rscreen);
+
struct r600_pipe_fences {
struct r600_resource *bo;
unsigned *data;
unsigned family;
enum chip_class chip_class;
struct radeon_info info;
+ bool has_streamout;
struct r600_tiling_info tiling_info;
- struct util_slab_mempool pool_buffers;
struct r600_pipe_fences fences;
- unsigned num_contexts;
bool use_surface_alloc;
int glsl_feature_level;
- /* for thread-safe write accessing to num_contexts */
- pipe_mutex mutex_num_contexts;
+ /*for compute global memory binding, we allocate stuff here, instead of
+ * buffers.
+ * XXX: Not sure if this is the best place for global_pool. Also,
+ * it's not thread safe, so it won't work with multiple contexts. */
+ struct compute_memory_pool *global_pool;
};
struct r600_pipe_sampler_view {
struct r600_pipe_state rstate;
};
+struct r600_pipe_shader;
+
+struct r600_pipe_shader_selector {
+ struct r600_pipe_shader *current;
+
+ struct tgsi_token *tokens;
+ struct pipe_stream_output_info so;
+
+ unsigned num_shaders;
+
+ /* PIPE_SHADER_[VERTEX|FRAGMENT|...] */
+ unsigned type;
+
+ unsigned nr_ps_max_color_exports;
+};
+
struct r600_pipe_shader {
+ struct r600_pipe_shader_selector *selector;
+ struct r600_pipe_shader *next_variant;
struct r600_shader shader;
struct r600_pipe_state rstate;
struct r600_resource *bo;
struct r600_resource *bo_fetch;
struct r600_vertex_element vertex_elements;
- struct tgsi_token *tokens;
unsigned sprite_coord_enable;
unsigned flatshade;
unsigned pa_cl_vs_out_cntl;
- unsigned ps_cb_shader_mask;
- struct pipe_stream_output_info so;
+ unsigned nr_ps_color_outputs;
+ unsigned key;
+ unsigned db_shader_control;
+ unsigned ps_depth_export;
};
struct r600_pipe_sampler_state {
ubyte writemask[2];
};
-struct r600_constant_buffer
-{
- struct pipe_resource *buffer;
- unsigned buffer_offset;
- unsigned buffer_size;
-};
-
struct r600_constbuf_state
{
struct r600_atom atom;
- struct r600_constant_buffer cb[PIPE_MAX_CONSTANT_BUFFERS];
+ struct pipe_constant_buffer cb[PIPE_MAX_CONSTANT_BUFFERS];
uint32_t enabled_mask;
uint32_t dirty_mask;
};
struct r600_pipe_state *states[R600_PIPE_NSTATES];
struct r600_vertex_element *vertex_elements;
struct pipe_framebuffer_state framebuffer;
- unsigned cb_target_mask;
- unsigned fb_cb_shader_mask;
+ unsigned compute_cb_target_mask;
unsigned sx_alpha_test_control;
- unsigned cb_shader_mask;
- unsigned cb_color_control;
+ unsigned db_shader_control;
unsigned pa_sc_line_stipple;
unsigned pa_cl_clip_cntl;
/* for saving when using blitter */
struct pipe_stencil_ref stencil_ref;
struct pipe_viewport_state viewport;
struct pipe_clip_state clip;
- struct r600_pipe_shader *ps_shader;
- struct r600_pipe_shader *vs_shader;
+ struct r600_pipe_shader_selector *ps_shader;
+ struct r600_pipe_shader_selector *vs_shader;
+ struct r600_pipe_compute *cs_shader;
struct r600_pipe_rasterizer *rasterizer;
struct r600_pipe_state vgt;
struct r600_pipe_state spi;
unsigned saved_render_cond_mode;
/* shader information */
boolean two_side;
+ boolean spi_dirty;
unsigned sprite_coord_enable;
+ boolean flatshade;
boolean export_16bpc;
unsigned alpha_ref;
boolean alpha_ref_dirty;
/* States based on r600_atom. */
struct list_head dirty_states;
struct r600_command_buffer start_cs_cmd; /* invariant state mostly */
+ /** Compute specific registers initializations. The start_cs_cmd atom
+ * must be emitted before start_compute_cs_cmd. */
+ struct r600_command_buffer start_compute_cs_cmd;
struct r600_surface_sync_cmd surface_sync_cmd;
struct r600_atom r6xx_flush_and_inv_cmd;
+ struct r600_cb_misc_state cb_misc_state;
struct r600_db_misc_state db_misc_state;
struct r600_atom vertex_buffer_state;
struct r600_constbuf_state vs_constbuf_state;
void *dummy_pixel_shader;
boolean dual_src_blend;
- unsigned color0_format;
/* Vertex and index buffers. */
bool vertex_buffers_dirty;
enum pipe_texture_target target,
unsigned sample_count,
unsigned usage);
+void evergreen_cb(struct r600_context *rctx, struct r600_pipe_state *rstate,
+ const struct pipe_framebuffer_state *state, int cb);
+
+
+void evergreen_update_dual_export_state(struct r600_context * rctx);
/* r600_blit.c */
void r600_init_blit_functions(struct r600_context *rctx);
-void r600_blit_uncompress_depth(struct pipe_context *ctx, struct r600_resource_texture *texture);
-void r600_blit_push_depth(struct pipe_context *ctx, struct r600_resource_texture *texture);
+void r600_blit_uncompress_depth(struct pipe_context *ctx,
+ struct r600_resource_texture *texture,
+ struct r600_resource_texture *staging);
void r600_flush_depth_textures(struct r600_context *rctx);
/* r600_buffer.c */
unsigned bind, unsigned usage);
struct pipe_resource *r600_buffer_create(struct pipe_screen *screen,
const struct pipe_resource *templ);
-struct pipe_resource *r600_user_buffer_create(struct pipe_screen *screen,
- void *ptr, unsigned bytes,
- unsigned bind);
/* r600_pipe.c */
void r600_flush(struct pipe_context *ctx, struct pipe_fence_handle **fence,
/* r600_shader.c */
int r600_pipe_shader_create(struct pipe_context *ctx, struct r600_pipe_shader *shader);
+#ifdef HAVE_OPENCL
+int r600_compute_shader_create(struct pipe_context * ctx,
+ LLVMModuleRef mod, struct r600_bytecode * bytecode);
+#endif
void r600_pipe_shader_destroy(struct pipe_context *ctx, struct r600_pipe_shader *shader);
-int r600_find_vs_semantic_index(struct r600_shader *vs,
- struct r600_shader *ps, int id);
/* r600_state.c */
void r600_set_scissor_state(struct r600_context *rctx,
enum pipe_texture_target target,
unsigned sample_count,
unsigned usage);
+void r600_update_dual_export_state(struct r600_context * rctx);
/* r600_texture.c */
void r600_init_screen_texture_functions(struct pipe_screen *screen);
struct pipe_sampler_view *state);
void r600_delete_state(struct pipe_context *ctx, void *state);
void r600_bind_vertex_elements(struct pipe_context *ctx, void *state);
-void *r600_create_shader_state(struct pipe_context *ctx,
- const struct pipe_shader_state *state);
+void *r600_create_shader_state_ps(struct pipe_context *ctx,
+ const struct pipe_shader_state *state);
+void *r600_create_shader_state_vs(struct pipe_context *ctx,
+ const struct pipe_shader_state *state);
void r600_bind_ps_shader(struct pipe_context *ctx, void *state);
void r600_bind_vs_shader(struct pipe_context *ctx, void *state);
void r600_delete_ps_shader(struct pipe_context *ctx, void *state);
void r600_delete_vs_shader(struct pipe_context *ctx, void *state);
void r600_constant_buffers_dirty(struct r600_context *rctx, struct r600_constbuf_state *state);
void r600_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index,
- struct pipe_resource *buffer);
+ struct pipe_constant_buffer *cb);
struct pipe_stream_output_target *
r600_create_so_target(struct pipe_context *ctx,
struct pipe_resource *buffer,
cb->buf[cb->atom.num_dw++] = (reg - R600_CONFIG_REG_OFFSET) >> 2;
}
+/**
+ * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute
+ * shaders.
+ */
static INLINE void r600_store_context_reg_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
{
assert(reg >= R600_CONTEXT_REG_OFFSET && reg < R600_CTL_CONST_OFFSET);
assert(cb->atom.num_dw+2+num <= cb->max_num_dw);
- cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_CONTEXT_REG, num, 0);
+ cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_CONTEXT_REG, num, 0) | cb->pkt_flags;
cb->buf[cb->atom.num_dw++] = (reg - R600_CONTEXT_REG_OFFSET) >> 2;
}
+/**
+ * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute
+ * shaders.
+ */
static INLINE void r600_store_ctl_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
{
assert(reg >= R600_CTL_CONST_OFFSET);
assert(cb->atom.num_dw+2+num <= cb->max_num_dw);
- cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_CTL_CONST, num, 0);
+ cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_CTL_CONST, num, 0) | cb->pkt_flags;
cb->buf[cb->atom.num_dw++] = (reg - R600_CTL_CONST_OFFSET) >> 2;
}
cb->buf[cb->atom.num_dw++] = (reg - R600_LOOP_CONST_OFFSET) >> 2;
}
+/**
+ * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute
+ * shaders.
+ */
static INLINE void eg_store_loop_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
{
assert(reg >= EG_LOOP_CONST_OFFSET);
assert(cb->atom.num_dw+2+num <= cb->max_num_dw);
- cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_LOOP_CONST, num, 0);
+ cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_LOOP_CONST, num, 0) | cb->pkt_flags;
cb->buf[cb->atom.num_dw++] = (reg - EG_LOOP_CONST_OFFSET) >> 2;
}
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