#include "amdtp.h"
#include "iso-resources.h"
#include "lib.h"
-
-#define DICE_PRIVATE_SPACE 0xffffe0000000uLL
-
-/* offset from DICE_PRIVATE_SPACE; offsets and sizes in quadlets */
-#define DICE_GLOBAL_OFFSET 0x00
-#define DICE_GLOBAL_SIZE 0x04
-#define DICE_TX_OFFSET 0x08
-#define DICE_TX_SIZE 0x0c
-#define DICE_RX_OFFSET 0x10
-#define DICE_RX_SIZE 0x14
-
-/* pointed to by DICE_GLOBAL_OFFSET */
-#define GLOBAL_OWNER 0x000
-#define OWNER_NO_OWNER 0xffff000000000000uLL
-#define OWNER_NODE_SHIFT 48
-#define GLOBAL_NOTIFICATION 0x008
-#define NOTIFY_RX_CFG_CHG 0x00000001
-#define NOTIFY_TX_CFG_CHG 0x00000002
-#define NOTIFY_DUP_ISOC 0x00000004
-#define NOTIFY_BW_ERR 0x00000008
-#define NOTIFY_LOCK_CHG 0x00000010
-#define NOTIFY_CLOCK_ACCEPTED 0x00000020
-#define NOTIFY_INTERFACE_CHG 0x00000040
-#define NOTIFY_MESSAGE 0x00100000
-#define GLOBAL_NICK_NAME 0x00c
-#define NICK_NAME_SIZE 64
-#define GLOBAL_CLOCK_SELECT 0x04c
-#define CLOCK_SOURCE_MASK 0x000000ff
-#define CLOCK_SOURCE_AES1 0x00000000
-#define CLOCK_SOURCE_AES2 0x00000001
-#define CLOCK_SOURCE_AES3 0x00000002
-#define CLOCK_SOURCE_AES4 0x00000003
-#define CLOCK_SOURCE_AES_ANY 0x00000004
-#define CLOCK_SOURCE_ADAT 0x00000005
-#define CLOCK_SOURCE_TDIF 0x00000006
-#define CLOCK_SOURCE_WC 0x00000007
-#define CLOCK_SOURCE_ARX1 0x00000008
-#define CLOCK_SOURCE_ARX2 0x00000009
-#define CLOCK_SOURCE_ARX3 0x0000000a
-#define CLOCK_SOURCE_ARX4 0x0000000b
-#define CLOCK_SOURCE_INTERNAL 0x0000000c
-#define CLOCK_RATE_MASK 0x0000ff00
-#define CLOCK_RATE_32000 0x00000000
-#define CLOCK_RATE_44100 0x00000100
-#define CLOCK_RATE_48000 0x00000200
-#define CLOCK_RATE_88200 0x00000300
-#define CLOCK_RATE_96000 0x00000400
-#define CLOCK_RATE_176400 0x00000500
-#define CLOCK_RATE_192000 0x00000600
-#define CLOCK_RATE_ANY_LOW 0x00000700
-#define CLOCK_RATE_ANY_MID 0x00000800
-#define CLOCK_RATE_ANY_HIGH 0x00000900
-#define CLOCK_RATE_NONE 0x00000a00
-#define CLOCK_RATE_SHIFT 8
-#define GLOBAL_ENABLE 0x050
-#define ENABLE 0x00000001
-#define GLOBAL_STATUS 0x054
-#define STATUS_SOURCE_LOCKED 0x00000001
-#define STATUS_RATE_CONFLICT 0x00000002
-#define STATUS_NOMINAL_RATE_MASK 0x0000ff00
-#define GLOBAL_EXTENDED_STATUS 0x058
-#define EXT_STATUS_AES1_LOCKED 0x00000001
-#define EXT_STATUS_AES2_LOCKED 0x00000002
-#define EXT_STATUS_AES3_LOCKED 0x00000004
-#define EXT_STATUS_AES4_LOCKED 0x00000008
-#define EXT_STATUS_ADAT_LOCKED 0x00000010
-#define EXT_STATUS_TDIF_LOCKED 0x00000020
-#define EXT_STATUS_ARX1_LOCKED 0x00000040
-#define EXT_STATUS_ARX2_LOCKED 0x00000080
-#define EXT_STATUS_ARX3_LOCKED 0x00000100
-#define EXT_STATUS_ARX4_LOCKED 0x00000200
-#define EXT_STATUS_WC_LOCKED 0x00000400
-#define EXT_STATUS_AES1_SLIP 0x00010000
-#define EXT_STATUS_AES2_SLIP 0x00020000
-#define EXT_STATUS_AES3_SLIP 0x00040000
-#define EXT_STATUS_AES4_SLIP 0x00080000
-#define EXT_STATUS_ADAT_SLIP 0x00100000
-#define EXT_STATUS_TDIF_SLIP 0x00200000
-#define EXT_STATUS_ARX1_SLIP 0x00400000
-#define EXT_STATUS_ARX2_SLIP 0x00800000
-#define EXT_STATUS_ARX3_SLIP 0x01000000
-#define EXT_STATUS_ARX4_SLIP 0x02000000
-#define EXT_STATUS_WC_SLIP 0x04000000
-#define GLOBAL_SAMPLE_RATE 0x05c
-#define GLOBAL_VERSION 0x060
-#define GLOBAL_CLOCK_CAPABILITIES 0x064
-#define CLOCK_CAP_RATE_32000 0x00000001
-#define CLOCK_CAP_RATE_44100 0x00000002
-#define CLOCK_CAP_RATE_48000 0x00000004
-#define CLOCK_CAP_RATE_88200 0x00000008
-#define CLOCK_CAP_RATE_96000 0x00000010
-#define CLOCK_CAP_RATE_176400 0x00000020
-#define CLOCK_CAP_RATE_192000 0x00000040
-#define CLOCK_CAP_SOURCE_AES1 0x00010000
-#define CLOCK_CAP_SOURCE_AES2 0x00020000
-#define CLOCK_CAP_SOURCE_AES3 0x00040000
-#define CLOCK_CAP_SOURCE_AES4 0x00080000
-#define CLOCK_CAP_SOURCE_AES_ANY 0x00100000
-#define CLOCK_CAP_SOURCE_ADAT 0x00200000
-#define CLOCK_CAP_SOURCE_TDIF 0x00400000
-#define CLOCK_CAP_SOURCE_WC 0x00800000
-#define CLOCK_CAP_SOURCE_ARX1 0x01000000
-#define CLOCK_CAP_SOURCE_ARX2 0x02000000
-#define CLOCK_CAP_SOURCE_ARX3 0x04000000
-#define CLOCK_CAP_SOURCE_ARX4 0x08000000
-#define CLOCK_CAP_SOURCE_INTERNAL 0x10000000
-#define GLOBAL_CLOCK_SOURCE_NAMES 0x068
-#define CLOCK_SOURCE_NAMES_SIZE 256
-
-/* pointed to by DICE_TX_OFFSET */
-#define TX_NUMBER 0x000
-#define TX_SIZE 0x004
-/* repeated TX_NUMBER times, offset by TX_SIZE quadlets */
-#define TX_ISOCHRONOUS 0x008
-#define TX_NUMBER_AUDIO 0x00c
-#define TX_NUMBER_MIDI 0x010
-#define TX_SPEED 0x014
-#define TX_NAMES 0x018
-#define TX_NAMES_SIZE 256
-#define TX_AC3_CAPABILITIES 0x118
-#define TX_AC3_ENABLE 0x11c
-
-/* pointed to by DICE_RX_OFFSET */
-#define RX_NUMBER 0x000
-#define RX_SIZE 0x004
-/* repeated RX_NUMBER times, offset by RX_SIZE quadlets */
-#define RX_ISOCHRONOUS 0x008
-#define RX_SEQ_START 0x00c
-#define RX_NUMBER_AUDIO 0x010
-#define RX_NUMBER_MIDI 0x014
-#define RX_NAMES 0x018
-#define RX_NAMES_SIZE 256
-#define RX_AC3_CAPABILITIES 0x118
-#define RX_AC3_ENABLE 0x11c
-
-
-#define FIRMWARE_LOAD_SPACE 0xffffe0100000uLL
-
-/* offset from FIRMWARE_LOAD_SPACE */
-#define FIRMWARE_VERSION 0x000
-#define FIRMWARE_OPCODE 0x004
-#define OPCODE_MASK 0x00000fff
-#define OPCODE_GET_IMAGE_DESC 0x00000000
-#define OPCODE_DELETE_IMAGE 0x00000001
-#define OPCODE_CREATE_IMAGE 0x00000002
-#define OPCODE_UPLOAD 0x00000003
-#define OPCODE_UPLOAD_STAT 0x00000004
-#define OPCODE_RESET_IMAGE 0x00000005
-#define OPCODE_TEST_ACTION 0x00000006
-#define OPCODE_GET_RUNNING_IMAGE_VINFO 0x0000000a
-#define OPCODE_EXECUTE 0x80000000
-#define FIRMWARE_RETURN_STATUS 0x008
-#define FIRMWARE_PROGRESS 0x00c
-#define PROGRESS_CURR_MASK 0x00000fff
-#define PROGRESS_MAX_MASK 0x00fff000
-#define PROGRESS_TOUT_MASK 0x0f000000
-#define PROGRESS_FLAG 0x80000000
-#define FIRMWARE_CAPABILITIES 0x010
-#define FL_CAP_AUTOERASE 0x00000001
-#define FL_CAP_PROGRESS 0x00000002
-#define FIRMWARE_DATA 0x02c
-#define TEST_CMD_POKE 0x00000001
-#define TEST_CMD_PEEK 0x00000002
-#define CMD_GET_AVS_CNT 0x00000003
-#define CMD_CLR_AVS_CNT 0x00000004
-#define CMD_SET_MODE 0x00000005
-#define CMD_SET_MIDIBP 0x00000006
-#define CMD_GET_AVSPHASE 0x00000007
-#define CMD_ENABLE_BNC_SYNC 0x00000008
-#define CMD_PULSE_BNC_SYNC 0x00000009
-#define CMD_EMUL_SLOW_CMD 0x0000000a
-#define FIRMWARE_TEST_DELAY 0xfd8
-#define FIRMWARE_TEST_BUF 0xfdc
-
-
-/* EAP */
-#define EAP_PRIVATE_SPACE 0xffffe0200000uLL
-
-#define EAP_CAPABILITY_OFFSET 0x000
-#define EAP_CAPABILITY_SIZE 0x004
-/* ... */
-
-#define EAP_ROUTER_CAPS 0x000
-#define ROUTER_EXPOSED 0x00000001
-#define ROUTER_READ_ONLY 0x00000002
-#define ROUTER_FLASH 0x00000004
-#define MAX_ROUTES_MASK 0xffff0000
-#define EAP_MIXER_CAPS 0x004
-#define MIXER_EXPOSED 0x00000001
-#define MIXER_READ_ONLY 0x00000002
-#define MIXER_FLASH 0x00000004
-#define MIXER_IN_DEV_MASK 0x000000f0
-#define MIXER_OUT_DEV_MASK 0x00000f00
-#define MIXER_INPUTS_MASK 0x00ff0000
-#define MIXER_OUTPUTS_MASK 0xff000000
-#define EAP_GENERAL_CAPS 0x008
-#define GENERAL_STREAM_CONFIG 0x00000001
-#define GENERAL_FLASH 0x00000002
-#define GENERAL_PEAK 0x00000004
-#define GENERAL_MAX_TX_STREAMS_MASK 0x000000f0
-#define GENERAL_MAX_RX_STREAMS_MASK 0x00000f00
-#define GENERAL_STREAM_CONFIG_FLASH 0x00001000
-#define GENERAL_CHIP_MASK 0x00ff0000
-#define GENERAL_CHIP_DICE_II 0x00000000
-#define GENERAL_CHIP_DICE_MINI 0x00010000
-#define GENERAL_CHIP_DICE_JR 0x00020000
+#include "dice-interface.h"
struct dice {
__be32 value;
int rcode, err, errors = 0;
- value = cpu_to_be32(ENABLE);
+ value = cpu_to_be32(1);
for (;;) {
rcode = fw_run_transaction(device->card,
TCODE_WRITE_QUADLET_REQUEST,
mutex_destroy(&dice->mutex);
}
+#define DICE_CATEGORY_ID 0x04
+
+static int dice_interface_check(struct fw_unit *unit)
+{
+ static const int min_values[10] = {
+ 10, 0x64 / 4,
+ 10, 0x18 / 4,
+ 10, 0x18 / 4,
+ 0, 0,
+ 0, 0,
+ };
+ struct fw_device *device = fw_parent_device(unit);
+ struct fw_csr_iterator it;
+ int key, value, vendor = -1, model = -1, err;
+ unsigned int i;
+ __be32 pointers[ARRAY_SIZE(min_values)];
+ __be32 version;
+
+ /*
+ * Check that GUID and unit directory are constructed according to DICE
+ * rules, i.e., that the specifier ID is the GUID's OUI, and that the
+ * GUID chip ID consists of the 8-bit DICE category ID, the 10-bit
+ * product ID, and a 22-bit serial number.
+ */
+ fw_csr_iterator_init(&it, unit->directory);
+ while (fw_csr_iterator_next(&it, &key, &value)) {
+ switch (key) {
+ case CSR_SPECIFIER_ID:
+ vendor = value;
+ break;
+ case CSR_MODEL:
+ model = value;
+ break;
+ }
+ }
+ if (device->config_rom[3] != ((vendor << 8) | DICE_CATEGORY_ID) ||
+ device->config_rom[4] >> 22 != model)
+ return -ENODEV;
+
+ /*
+ * Check that the sub address spaces exist and are located inside the
+ * private address space. The minimum values are chosen so that all
+ * minimally required registers are included.
+ */
+ err = snd_fw_transaction(unit, TCODE_READ_BLOCK_REQUEST,
+ DICE_PRIVATE_SPACE,
+ pointers, sizeof(pointers));
+ if (err < 0)
+ return -ENODEV;
+ for (i = 0; i < ARRAY_SIZE(pointers); ++i) {
+ value = be32_to_cpu(pointers[i]);
+ if (value < min_values[i] || value >= 0x40000)
+ return -ENODEV;
+ }
+
+ /*
+ * Check that the implemented DICE driver specification major version
+ * number matches.
+ */
+ err = snd_fw_transaction(unit, TCODE_READ_QUADLET_REQUEST,
+ DICE_PRIVATE_SPACE +
+ be32_to_cpu(pointers[0]) * 4 + GLOBAL_VERSION,
+ &version, 4);
+ if (err < 0)
+ return -ENODEV;
+ if ((version & cpu_to_be32(0xff000000)) != cpu_to_be32(0x01000000)) {
+ dev_err(&unit->device,
+ "unknown DICE version: 0x%08x\n", be32_to_cpu(version));
+ return -ENODEV;
+ }
+
+ return 0;
+}
+
static int dice_init_offsets(struct dice *dice)
{
__be32 pointers[6];
- unsigned int global_size, rx_size;
int err;
err = snd_fw_transaction(dice->unit, TCODE_READ_BLOCK_REQUEST,
- DICE_PRIVATE_SPACE, &pointers, 6 * 4);
+ DICE_PRIVATE_SPACE,
+ pointers, sizeof(pointers));
if (err < 0)
return err;
dice->global_offset = be32_to_cpu(pointers[0]) * 4;
- global_size = be32_to_cpu(pointers[1]);
dice->rx_offset = be32_to_cpu(pointers[4]) * 4;
- rx_size = be32_to_cpu(pointers[5]);
-
- /* some sanity checks to ensure that we actually have a DICE */
- if (dice->global_offset < 10 * 4 || global_size < 0x168 / 4 ||
- dice->rx_offset < 10 * 4 || rx_size < 0x120 / 4) {
- dev_err(&dice->unit->device, "invalid register pointers\n");
- return -ENXIO;
- }
return 0;
}
strcpy(model, "?");
fw_csr_string(dice->unit->directory, CSR_MODEL, model, sizeof(model));
snprintf(card->longname, sizeof(card->longname),
- "%s %s, GUID %08x%08x at %s, S%d",
- vendor, model, dev->config_rom[3], dev->config_rom[4],
+ "%s %s (serial %u) at %s, S%d",
+ vendor, model, dev->config_rom[4] & 0x3fffff,
dev_name(&dice->unit->device), 100 << dev->max_speed);
strcpy(card->mixername, "DICE");
__be32 clock_sel;
int err;
+ err = dice_interface_check(unit);
+ if (err < 0)
+ return err;
+
err = snd_card_create(-1, NULL, THIS_MODULE, sizeof(*dice), &card);
if (err < 0)
return err;
mutex_unlock(&dice->mutex);
}
-#define TC_OUI 0x000166
#define DICE_INTERFACE 0x000001
static const struct ieee1394_device_id dice_id_table[] = {
{
- .match_flags = IEEE1394_MATCH_SPECIFIER_ID |
- IEEE1394_MATCH_VERSION,
- .specifier_id = TC_OUI,
- .version = DICE_INTERFACE,
+ .match_flags = IEEE1394_MATCH_VERSION,
+ .version = DICE_INTERFACE,
},
{ }
};
projects / platform / adaptation / renesas_rcar / renesas_kernel.git / blobdiff