-:option::insn-bit-size:16
-:option::hi-bit-nr:15
+:option:::insn-bit-size:16
+:option:::hi-bit-nr:15
-:option::format-names:I,II,III,IV,V,VI,VII,VIII,IX,X
-# start-sanitize-v850e
-:option::format-names:XI,XII,XIII
-# end-sanitize-v850e
-# start-sanitize-v850eq
-:option::format-names:XIV,XV
-# end-sanitize-v850eq
-:option::format-names:Z
+:option:::format-names:I,II,III,IV,V,VI,VII,VIII,IX,X
+:option:::format-names:XI,XII,XIII
+:option:::format-names:XIV,XV
+:option:::format-names:Z
-:model::v850:v850:
+:model:::v850:v850:
-# start-sanitize-v850e
-:option::multi-sim:true
-:model::v850e:v850e:
-# end-sanitize-v850e
+:option:::multi-sim:true
+:model:::v850e:v850e:
-# start-sanitize-v850eq
-:option::multi-sim:true
-:model::v850eq:v850eq:
-# end-sanitize-v850eq
+:option:::multi-sim:true
+:model:::v850ea:v850ea:
// Cache macros
-:cache::unsigned:reg1:RRRRR:(RRRRR)
-:cache::unsigned:reg2:rrrrr:(rrrrr)
-:cache::unsigned:reg3:wwwww:(wwwww)
-:cache::unsigned:regID:rrrrr:(rrrrr)
-
-:cache::unsigned:disp4:dddd:(dddd)
-# start-sanitize-v850e
-:cache::unsigned:disp5:dddd:(dddd << 1)
-# end-sanitize-v850e
-:cache::unsigned:disp7:ddddddd:ddddddd
-:cache::unsigned:disp8:ddddddd:(ddddddd << 1)
-:cache::unsigned:disp8:dddddd:(dddddd << 2)
-:cache::unsigned:disp9:ddddd,ddd:SEXT32 ((ddddd << 4) + (ddd << 1), 9 - 1)
-:cache::unsigned:disp16:dddddddddddddddd:SEXT32 (dddddddddddddddd, 16 - 1)
-:cache::unsigned:disp16:ddddddddddddddd:SEXT32 (ddddddddddddddd << 1, 16 - 1)
-:cache::unsigned:disp22:dddddd,dddddddddddddddd:SEXT32 ((dddddd << 16) + (dddddddddddddddd << 1), 22 - 1)
-:cache::unsigned:disp22:dddddd,ddddddddddddddd:SEXT32 ((dddddd << 16) + (ddddddddddddddd << 2), 22 - 1)
-
-:cache::unsigned:imm5:iiiii:SEXT32 (iiiii, 4)
-:cache::unsigned:imm6:iiiiii:iiiiii
-:cache::unsigned:imm9:iiiii,IIII:SEXT ((IIII << 5) + iiiii, 9 - 1)
-# start-sanitize-v850eq
-:cache::unsigned:imm5:iiii:(32 - (iiii << 1))
-# end-sanitize-v850eq
-:cache::unsigned:imm16:iiiiiiiiiiiiiiii:iiiiiiiiiiiiiiii
-:cache::unsigned:imm32:iiiiiiiiiiiiiiii,IIIIIIIIIIIIIIII:(iiiiiiiiiiiiiiii < 16 + IIIIIIIIIIIIIIII)
-# start-sanitize-v850e
-:cache::unsigned:uimm16:iiiiiiiiiiiiiiii:iiiiiiiiiiiiiiii
-:cache::unsigned:uimm32:iiiiiiiiiiiiiiii,dddddddddddddddd:((iiiiiiiiiiiiiiii << 16) + dddddddddddddddd)
-# end-sanitize-v850e
-
-:cache::unsigned:vector:iiiii:iiiii
-
-# start-sanitize-v850e
-:cache::unsigned:list12:L,LLLLLLLLLLL:((L << 11) + LLLLLLLLLLL)
-:cache::unsigned:list18:LLLL,LLLLLLLLLLLL:((LLLL << 12) + LLLLLLLLLLLL)
-# end-sanitize-v850e
-
-:cache::unsigned:bit3:bbb:bbb
+:cache:::unsigned:reg1:RRRRR:(RRRRR)
+:cache:::unsigned:reg2:rrrrr:(rrrrr)
+:cache:::unsigned:reg3:wwwww:(wwwww)
+
+:cache:::unsigned:disp4:dddd:(dddd)
+:cache:::unsigned:disp5:dddd:(dddd << 1)
+:cache:::unsigned:disp7:ddddddd:ddddddd
+:cache:::unsigned:disp8:ddddddd:(ddddddd << 1)
+:cache:::unsigned:disp8:dddddd:(dddddd << 2)
+:cache:::unsigned:disp9:ddddd,ddd:SEXT32 ((ddddd << 4) + (ddd << 1), 9 - 1)
+:cache:::unsigned:disp16:dddddddddddddddd:EXTEND16 (dddddddddddddddd)
+:cache:::unsigned:disp16:ddddddddddddddd: EXTEND16 (ddddddddddddddd << 1)
+:cache:::unsigned:disp22:dddddd,ddddddddddddddd: SEXT32 ((dddddd << 16) + (ddddddddddddddd << 1), 22 - 1)
+
+:cache:::unsigned:imm5:iiiii:SEXT32 (iiiii, 4)
+:cache:::unsigned:imm6:iiiiii:iiiiii
+:cache:::unsigned:imm9:iiiii,IIII:SEXT ((IIII << 5) + iiiii, 9 - 1)
+:cache:::unsigned:imm5:iiii:(32 - (iiii << 1))
+:cache:::unsigned:simm16:iiiiiiiiiiiiiiii:EXTEND16 (iiiiiiiiiiiiiiii)
+:cache:::unsigned:uimm16:iiiiiiiiiiiiiiii:iiiiiiiiiiiiiiii
+:cache:::unsigned:imm32:iiiiiiiiiiiiiiii,IIIIIIIIIIIIIIII:(iiiiiiiiiiiiiiii < 16 + IIIIIIIIIIIIIIII)
+:cache:::unsigned:uimm32:iiiiiiiiiiiiiiii,dddddddddddddddd:((iiiiiiiiiiiiiiii << 16) + dddddddddddddddd)
+
+:cache:::unsigned:vector:iiiii:iiiii
+
+:cache:::unsigned:list12:L,LLLLLLLLLLL:((L << 11) + LLLLLLLLLLL)
+:cache:::unsigned:list18:LLLL,LLLLLLLLLLLL:((LLLL << 12) + LLLLLLLLLLLL)
+
+:cache:::unsigned:bit3:bbb:bbb
// What do we do with an illegal instruction?
-:internal:::illegal
+:internal::::illegal:
{
sim_io_eprintf (SD, "Illegal instruction at address 0x%lx\n",
(unsigned long) cia);
- sim_engine_halt (SD, CPU, NULL, cia, sim_signalled, SIGILL);
+ sim_engine_halt (SD, CPU, NULL, cia, sim_signalled, SIM_SIGILL);
}
// ADDI
rrrrr,110000,RRRRR + iiiiiiiiiiiiiiii:VI:::addi
-"addi <imm16>, r<reg1>, r<reg2>"
+"addi <simm16>, r<reg1>, r<reg2>"
{
COMPAT_2 (OP_600 ());
}
// ANDI
rrrrr,110110,RRRRR + iiiiiiiiiiiiiiii:VI:::andi
-"andi <imm16>, r<reg1>, r<reg2>"
+"andi <uimm16>, r<reg1>, r<reg2>"
{
COMPAT_2 (OP_6C0 ());
}
-// Bcond
-// ddddd,1011,ddd,cccc:III:::Bcond
-// "b<cond> disp9"
-
-ddddd,1011,ddd,0000:III:::bv
-"bv <disp9>"
-{
- COMPAT_1 (OP_580 ());
-}
-
-ddddd,1011,ddd,0001:III:::bl
-"bl <disp9>"
-{
- COMPAT_1 (OP_581 ());
-}
-
-ddddd,1011,ddd,0010:III:::be
-"be <disp9>"
-{
- COMPAT_1 (OP_582 ());
-}
-
-ddddd,1011,ddd,0011:III:::bnh
-"bnh <disp9>"
-{
- COMPAT_1 (OP_583 ());
-}
-
-ddddd,1011,ddd,0100:III:::bn
-"bn <disp9>"
-{
- COMPAT_1 (OP_584 ());
-}
-
-ddddd,1011,ddd,0101:III:::br
-"br <disp9>"
-{
- COMPAT_1 (OP_585 ());
-}
-
-ddddd,1011,ddd,0110:III:::blt
-"blt <disp9>"
-{
- COMPAT_1 (OP_586 ());
-}
-
-ddddd,1011,ddd,0111:III:::ble
-"ble <disp9>"
+// Map condition code to a string
+:%s::::cccc:int cccc
{
- COMPAT_1 (OP_587 ());
-}
+ switch (cccc)
+ {
+ case 0xf: return "gt";
+ case 0xe: return "ge";
+ case 0x6: return "lt";
-ddddd,1011,ddd,1000:III:::bnv
-"bnv <disp9>"
-{
- COMPAT_1 (OP_588 ());
-}
+ case 0x7: return "le";
-ddddd,1011,ddd,1001:III:::bnl
-"bnl <disp9>"
-{
- COMPAT_1 (OP_589 ());
-}
+ case 0xb: return "h";
+ case 0x9: return "nl";
+ case 0x1: return "l";
-ddddd,1011,ddd,1010:III:::bne
-"bne <disp9>"
-{
- COMPAT_1 (OP_58A ());
-}
+ case 0x3: return "nh";
-ddddd,1011,ddd,1011:III:::bh
-"bh <disp9>"
-{
- COMPAT_1 (OP_58B ());
-}
+ case 0x2: return "e";
-ddddd,1011,ddd,1100:III:::bp
-"bp <disp9>"
-{
- COMPAT_1 (OP_58C ());
-}
+ case 0xa: return "ne";
-ddddd,1011,ddd,1101:III:::bsa
-"bsa <disp9>"
-{
- COMPAT_1 (OP_58D ());
+ case 0x0: return "v";
+ case 0x8: return "nv";
+ case 0x4: return "n";
+ case 0xc: return "p";
+ /* case 0x1: return "c"; */
+ /* case 0x9: return "nc"; */
+ /* case 0x2: return "z"; */
+ /* case 0xa: return "nz"; */
+ case 0x5: return "r"; /* always */
+ case 0xd: return "sa";
+ }
+ return "(null)";
}
-ddddd,1011,ddd,1110:III:::bge
-"bge <disp9>"
-{
- COMPAT_1 (OP_58E ());
-}
-ddddd,1011,ddd,1111:III:::bgt
-"bgt <disp9>"
+// Bcond
+ddddd,1011,ddd,cccc:III:::Bcond
+"b%s<cccc> <disp9>"
{
- COMPAT_1 (OP_58F ());
+ int cond;
+ if ((ddddd == 0x00) && (ddd == 0x00) && (cccc == 0x05)) {
+ // Special case - treat "br *" like illegal instruction
+ sim_engine_halt (SD, CPU, NULL, cia, sim_stopped, SIM_SIGTRAP);
+ } else {
+ cond = condition_met (cccc);
+ if (cond)
+ nia = cia + disp9;
+ TRACE_BRANCH1 (cond);
+ }
}
-// start-sanitize-v850e
// BSH
rrrrr,11111100000 + wwwww,01101000010:XII:::bsh
*v850e
-// start-sanitize-v850eq
-*v850eq
-// end-sanitize-v850eq
+*v850ea
"bsh r<reg2>, r<reg3>"
{
- COMPAT_2 (OP_34207E0 ());
-}
+ unsigned32 value;
+ TRACE_ALU_INPUT1 (GR[reg2]);
+ value = (MOVED32 (GR[reg2], 23, 16, 31, 24)
+ | MOVED32 (GR[reg2], 31, 24, 23, 16)
+ | MOVED32 (GR[reg2], 7, 0, 15, 8)
+ | MOVED32 (GR[reg2], 15, 8, 7, 0));
+ GR[reg3] = value;
+ PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
+ if (value == 0) PSW |= PSW_Z;
+ if (value & 0x80000000) PSW |= PSW_S;
+ if (((value & 0xff) == 0) || (value & 0x00ff) == 0) PSW |= PSW_CY;
+
+ TRACE_ALU_RESULT (GR[reg3]);
+}
-// end-sanitize-v850e
-// start-sanitize-v850e
// BSW
rrrrr,11111100000 + wwwww,01101000000:XII:::bsw
*v850e
-// start-sanitize-v850eq
-*v850eq
-// end-sanitize-v850eq
-"bsw r<reg2>, reg3>"
+*v850ea
+"bsw r<reg2>, r<reg3>"
{
- COMPAT_2 (OP_34007E0 ());
-}
+#define WORDHASNULLBYTE(x) (((x) - 0x01010101) & ~(x)&0x80808080)
+ unsigned32 value;
+ TRACE_ALU_INPUT1 (GR[reg2]);
+
+ value = GR[reg2];
+ value >>= 24;
+ value |= (GR[reg2] << 24);
+ value |= ((GR[reg2] << 8) & 0x00ff0000);
+ value |= ((GR[reg2] >> 8) & 0x0000ff00);
+ GR[reg3] = value;
+ PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
+ if (value == 0) PSW |= PSW_Z;
+ if (value & 0x80000000) PSW |= PSW_S;
+ if (WORDHASNULLBYTE (value)) PSW |= PSW_CY;
+
+ TRACE_ALU_RESULT (GR[reg3]);
+}
-// end-sanitize-v850e
-// start-sanitize-v850e
// CALLT
0000001000,iiiiii:II:::callt
*v850e
-// start-sanitize-v850eq
-*v850eq
-// end-sanitize-v850eq
+*v850ea
"callt <imm6>"
{
- COMPAT_1 (OP_200 ());
+ unsigned32 adr;
+ unsigned32 off;
+ CTPC = cia + 2;
+ CTPSW = PSW;
+ adr = (CTBP & ~1) + (imm6 << 1);
+ off = load_mem (adr, 2) & ~1; /* Force alignment */
+ nia = (CTBP & ~1) + off;
+ TRACE_BRANCH3 (adr, CTBP, off);
}
-
-// end-sanitize-v850e
// CLR1
10,bbb,111110,RRRRR + dddddddddddddddd:VIII:::clr1
"clr1 <bit3>, <disp16>[r<reg1>]"
COMPAT_2 (OP_87C0 ());
}
-// start-sanitize-v850e
rrrrr,111111,RRRRR + 0000000011100100:IX:::clr1
*v850e
-// start-sanitize-v850eq
-*v850eq
-// end-sanitize-v850eq
+*v850ea
"clr1 r<reg2>, [r<reg1>]"
{
COMPAT_2 (OP_E407E0 ());
}
-
-// end-sanitize-v850e
-// start-sanitize-v850e
// CTRET
0000011111100000 + 0000000101000100:X:::ctret
*v850e
-// start-sanitize-v850eq
-*v850eq
-// end-sanitize-v850eq
+*v850ea
"ctret"
{
- COMPAT_2 (OP_14407E0 ());
+ nia = (CTPC & ~1);
+ PSW = (CTPSW & (CPU)->psw_mask);
+ TRACE_BRANCH1 (PSW);
}
-
-
-// end-sanitize-v850e
-// start-sanitize-v850e
// CMOV
rrrrr,111111,RRRRR + wwwww,011001,cccc,0:XI:::cmov
*v850e
-// start-sanitize-v850eq
-*v850eq
-// end-sanitize-v850eq
-"cmov <cccc>, r<reg1>, r<reg2>, r<reg3>"
+*v850ea
+"cmov %s<cccc>, r<reg1>, r<reg2>, r<reg3>"
{
- COMPAT_2 (OP_32007E0 ());
+ int cond = condition_met (cccc);
+ TRACE_ALU_INPUT3 (cond, GR[reg1], GR[reg2]);
+ GR[reg3] = cond ? GR[reg1] : GR[reg2];
+ TRACE_ALU_RESULT (GR[reg3]);
}
-// end-sanitize-v850e
-// start-sanitize-v850e
rrrrr,111111,iiiii + wwwww,011000,cccc,0:XII:::cmov
*v850e
-// start-sanitize-v850eq
-*v850eq
-// end-sanitize-v850eq
-"cmov <cccc>, <imm5>, r<reg2>, r<reg3>"
+*v850ea
+"cmov %s<cccc>, <imm5>, r<reg2>, r<reg3>"
{
- COMPAT_2 (OP_30007E0 ());
+ int cond = condition_met (cccc);
+ TRACE_ALU_INPUT3 (cond, imm5, GR[reg2]);
+ GR[reg3] = cond ? imm5 : GR[reg2];
+ TRACE_ALU_RESULT (GR[reg3]);
}
-
-
-// end-sanitize-v850e
// CMP
rrrrr,001111,RRRRR:I:::cmp
"cmp r<reg1>, r<reg2>"
-// start-sanitize-v850e
// DISPOSE
// 0000011001,iiiii,L + LLLLLLLLLLL,00000:XIII:::dispose
// "dispose <imm5>, <list12>"
0000011001,iiiii,L + LLLLLLLLLLL,RRRRR:XIII:::dispose
*v850e
-// start-sanitize-v850eq
-*v850eq
-// end-sanitize-v850eq
+*v850ea
"dispose <imm5>, <list12>":RRRRR == 0
"dispose <imm5>, <list12>, [reg1]"
{
- COMPAT_2 (OP_640 ());
-}
+ int i;
+ SAVE_2;
+
+ trace_input ("dispose", OP_PUSHPOP1, 0);
+
+ SP += (OP[3] & 0x3e) << 1;
+ /* Load the registers with lower number registers being retrieved
+ from higher addresses. */
+ for (i = 12; i--;)
+ if ((OP[3] & (1 << type1_regs[ i ])))
+ {
+ State.regs[ 20 + i ] = load_mem (SP, 4);
+ SP += 4;
+ }
+
+ if ((OP[3] & 0x1f0000) != 0)
+ {
+ nia = State.regs[ (OP[3] >> 16) & 0x1f];
+ }
+
+ trace_output (OP_PUSHPOP1);
+}
-// end-sanitize-v850e
-// start-sanitize-v850e
// DIV
rrrrr,111111,RRRRR + wwwww,01011000000:XI:::div
*v850e
}
-
-
-// end-sanitize-v850e
// DIVH
rrrrr!0,000010,RRRRR!0:I:::divh
"divh r<reg1>, r<reg2>"
COMPAT_1 (OP_40 ());
}
-// start-sanitize-v850e
rrrrr,111111,RRRRR + wwwww,01010000000:XI:::divh
*v850e
"divh r<reg1>, r<reg2>, r<reg3>"
}
-
-// end-sanitize-v850e
-// start-sanitize-v850e
// DIVHU
rrrrr,111111,RRRRR + wwwww,01010000010:XI:::divhu
*v850e
}
-
-// end-sanitize-v850e
-// start-sanitize-v850e
// DIVU
rrrrr,111111,RRRRR + wwwww,01011000010:XI:::divu
*v850e
}
-
-// end-sanitize-v850e
// EI
1000011111100000 + 0000000101100000:X:::ei
"ei"
-// start-sanitize-v850e
// HSW
rrrrr,11111100000 + wwwww,01101000100:XII:::hsw
*v850e
-// start-sanitize-v850eq
-*v850eq
-// end-sanitize-v850eq
+*v850ea
"hsw r<reg2>, r<reg3>"
{
- COMPAT_2 (OP_34407E0 ());
+ unsigned32 value;
+ TRACE_ALU_INPUT1 (GR[reg2]);
+
+ value = GR[reg2];
+ value >>= 16;
+ value |= (GR[reg2] << 16);
+
+ GR[reg3] = value;
+
+ PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
+
+ if (value == 0) PSW |= PSW_Z;
+ if (value & 0x80000000) PSW |= PSW_S;
+ if (((value & 0xffff) == 0) || (value & 0xffff0000) == 0) PSW |= PSW_CY;
+
+ TRACE_ALU_RESULT (GR[reg3]);
}
-// end-sanitize-v850e
// JARL
rrrrr!0,11110,dddddd + ddddddddddddddd,0:V:::jarl
"jarl <disp22>, r<reg2>"
{
- COMPAT_2 (OP_780 ());
+ GR[reg2] = nia;
+ nia = cia + disp22;
+ TRACE_BRANCH1 (GR[reg2]);
}
00000000011,RRRRR:I:::jmp
"jmp [r<reg1>]"
{
- SAVE_1;
- trace_input ("jmp", OP_REG, 0);
- nia = State.regs[ reg1 ];
- trace_output (OP_REG);
+ nia = GR[reg1] & ~1;
+ TRACE_BRANCH0 ();
}
0000011110,dddddd + ddddddddddddddd,0:V:::jr
"jr <disp22>"
{
- COMPAT_2 (OP_780 ());
+ nia = cia + disp22;
+ TRACE_BRANCH0 ();
}
// LD
rrrrr,111000,RRRRR + dddddddddddddddd:VII:::ld.b
-"ld.b <disp16>[r<reg1>, r<reg2>"
+"ld.b <disp16>[r<reg1>], r<reg2>"
{
COMPAT_2 (OP_700 ());
}
COMPAT_2 (OP_10720 ());
}
-// start-sanitize-v850e
rrrrr!0,11110,b,RRRRR + ddddddddddddddd,1:VII:::ld.bu
*v850e
-// start-sanitize-v850eq
-*v850eq
-// end-sanitize-v850eq
+*v850ea
"ld.bu <disp16>[r<reg1>], r<reg2>"
{
COMPAT_2 (OP_10780 ());
}
-// end-sanitize-v850e
-// start-sanitize-v850e
rrrrr!0,111111,RRRRR + ddddddddddddddd,1:VII:::ld.hu
*v850e
-// start-sanitize-v850eq
-*v850eq
-// end-sanitize-v850eq
+*v850ea
"ld.hu <disp16>[r<reg1>], r<reg2>"
{
COMPAT_2 (OP_107E0 ());
}
-// end-sanitize-v850e
// LDSR
-//rrrrr,111111,RRRRR + 0000000000100000:IX:::ldsr
-//"ldsr r<reg2>, r<regID>"
-//{
-// COMPAT_2 (OP_2007E0 ());
-//}
-rrrrr,111111,RRRRR + 0000000000100000:IX:::ldsr
-"ldsr r<reg1>, r<regID>"
+regID,111111,RRRRR + 0000000000100000:IX:::ldsr
+"ldsr r<reg1>, s<regID>"
{
- SAVE_2;
- trace_input ("ldsr", OP_LDSR, 0);
+ TRACE_ALU_INPUT1 (GR[reg1]);
- if (&PSW == &State.sregs[ regID ])
- PSW = (State.regs[ reg1 ] & (CPU)->psw_mask);
+ if (&PSW == &SR[regID])
+ PSW = (GR[reg1] & (CPU)->psw_mask);
else
- State.sregs[ regID ] = State.regs[ reg1 ];
+ SR[regID] = GR[reg1];
- trace_output (OP_LDSR);
+ TRACE_ALU_RESULT (SR[regID]);
}
rrrrr!0,000000,RRRRR:I:::mov
"mov r<reg1>, r<reg2>"
{
- COMPAT_1 (OP_0 ());
+ TRACE_ALU_INPUT0 ();
+ GR[reg2] = GR[reg1];
+ TRACE_ALU_RESULT (GR[reg2]);
}
+
rrrrr!0,010000,iiiii:II:::mov
"mov <imm5>, r<reg2>"
{
COMPAT_1 (OP_200 ());
}
-// start-sanitize-v850e
00000110001,RRRRR + iiiiiiiiiiiiiiii + IIIIIIIIIIIIIIII:VI:::mov
*v850e
-// start-sanitize-v850eq
-*v850eq
-// end-sanitize-v850eq
+*v850ea
"mov <imm32>, r<reg1>"
{
- COMPAT_2 (OP_620 ());
+ SAVE_2;
+ trace_input ("mov", OP_IMM_REG, 4);
+ State.regs[ OP[0] ] = load_mem (PC + 2, 4);
+ trace_output (OP_IMM_REG);
}
-// end-sanitize-v850e
// MOVEA
rrrrr!0,110001,RRRRR + iiiiiiiiiiiiiiii:VI:::movea
-"movea <imm16>, r<reg1>, r<reg2>"
+"movea <simm16>, r<reg1>, r<reg2>"
{
- COMPAT_2 (OP_620 ());
+ TRACE_ALU_INPUT2 (GR[reg1], simm16);
+ GR[reg2] = GR[reg1] + simm16;
+ TRACE_ALU_RESULT (GR[reg2]);
}
// MOVHI
rrrrr!0,110010,RRRRR + iiiiiiiiiiiiiiii:VI:::movhi
-"movhi <imm16>, r<reg1>, r<reg2>"
+"movhi <uimm16>, r<reg1>, r<reg2>"
{
COMPAT_2 (OP_640 ());
}
-// start-sanitize-v850e
// MUL
rrrrr,111111,RRRRR + wwwww,01000100000:XI:::mul
*v850e
-// start-sanitize-v850eq
-*v850eq
-// end-sanitize-v850eq
+*v850ea
"mul r<reg1>, r<reg2>, r<reg3>"
{
COMPAT_2 (OP_22007E0 ());
}
-// end-sanitize-v850e
-// start-sanitize-v850e
rrrrr,111111,iiiii + wwwww,01001,IIII,00:XII:::mul
*v850e
-// start-sanitize-v850eq
-*v850eq
-// end-sanitize-v850eq
+*v850ea
"mul <imm9>, r<reg2>, r<reg3>"
{
COMPAT_2 (OP_24007E0 ());
}
-
-// end-sanitize-v850e
// MULH
rrrrr!0,000111,RRRRR:I:::mulh
"mulh r<reg1>, r<reg2>"
// MULHI
rrrrr!0,110111,RRRRR + iiiiiiiiiiiiiiii:VI:::mulhi
-"mulhi <imm16>, r<reg1>, r<reg2>"
+"mulhi <uimm16>, r<reg1>, r<reg2>"
{
COMPAT_2 (OP_6E0 ());
}
-// start-sanitize-v850e
// MULU
rrrrr,111111,RRRRR + wwwww,01000100010:XI:::mulu
*v850e
-// start-sanitize-v850eq
-*v850eq
-// end-sanitize-v850eq
+*v850ea
"mulu r<reg1>, r<reg2>, r<reg3>"
{
COMPAT_2 (OP_22207E0 ());
rrrrr,111111,iiiii + wwwww,01001,IIII,10:XII:::mulu
*v850e
-// start-sanitize-v850eq
-*v850eq
-// end-sanitize-v850eq
+*v850ea
"mulu <imm9>, r<reg2>, r<reg3>"
{
COMPAT_2 (OP_24207E0 ());
-// end-sanitize-v850e
// NOP
0000000000000000:I:::nop
"nop"
{
- COMPAT_1 (OP_0 ());
+ /* do nothing, trace nothing */
}
COMPAT_2 (OP_47C0 ());
}
-// start-sanitize-v850e
rrrrr,111111,RRRRR + 0000000011100010:IX:::not1
*v850e
-// start-sanitize-v850eq
-*v850eq
-// end-sanitize-v850eq
+*v850ea
"not1 r<reg2>, r<reg1>"
{
COMPAT_2 (OP_E207E0 ());
-// end-sanitize-v850e
// OR
rrrrr,001000,RRRRR:I:::or
"or r<reg1>, r<reg2>"
// ORI
rrrrr,110100,RRRRR + iiiiiiiiiiiiiiii:VI:::ori
-"ori <imm16>, r<reg1>, r<reg2>"
+"ori <uimm16>, r<reg1>, r<reg2>"
{
COMPAT_2 (OP_680 ());
}
-// start-sanitize-v850e
// PREPARE
0000011110,iiiii,L + LLLLLLLLLLL,00001:XIII:::prepare
*v850e
-// start-sanitize-v850eq
-*v850eq
-// end-sanitize-v850eq
+*v850ea
"prepare <list12>, <imm5>"
{
int i;
0000011110,iiiii,L + LLLLLLLLLLL,00011:XIII:::prepare00
*v850e
-// start-sanitize-v850eq
-*v850eq
-// end-sanitize-v850eq
+*v850ea
"prepare <list12>, <imm5>, sp"
{
COMPAT_2 (OP_30780 ());
0000011110,iiiii,L + LLLLLLLLLLL,01011 + iiiiiiiiiiiiiiii:XIII:::prepare01
*v850e
-// start-sanitize-v850eq
-*v850eq
-// end-sanitize-v850eq
+*v850ea
"prepare <list12>, <imm5>, <uimm16>"
{
COMPAT_2 (OP_B0780 ());
0000011110,iiiii,L + LLLLLLLLLLL,10011 + iiiiiiiiiiiiiiii:XIII:::prepare10
*v850e
-// start-sanitize-v850eq
-*v850eq
-// end-sanitize-v850eq
+*v850ea
"prepare <list12>, <imm5>, <uimm16>"
{
COMPAT_2 (OP_130780 ());
0000011110,iiiii,L + LLLLLLLLLLL,11011 + iiiiiiiiiiiiiiii + dddddddddddddddd:XIII:::prepare11
*v850e
-// start-sanitize-v850eq
-*v850eq
-// end-sanitize-v850eq
+*v850ea
"prepare <list12>, <imm5>, <uimm32>"
{
COMPAT_2 (OP_1B0780 ());
-// end-sanitize-v850e
// RETI
0000011111100000 + 0000000101000000:X:::reti
"reti"
{
- COMPAT_2 (OP_14007E0 ());
+ if ((PSW & PSW_EP))
+ {
+ nia = (EIPC & ~1);
+ PSW = EIPSW;
+ }
+ else if ((PSW & PSW_NP))
+ {
+ nia = (FEPC & ~1);
+ PSW = FEPSW;
+ }
+ else
+ {
+ nia = (EIPC & ~1);
+ PSW = EIPSW;
+ }
+ TRACE_BRANCH1 (PSW);
}
-// start-sanitize-v850e
// SASF
rrrrr,1111110,cccc + 0000001000000000:IX:::sasf
*v850e
-// start-sanitize-v850eq
-*v850eq
-// end-sanitize-v850eq
-"sasf <cccc>, r<reg2>"
+*v850ea
+"sasf %s<cccc>, r<reg2>"
{
COMPAT_2 (OP_20007E0 ());
}
-// end-sanitize-v850e
// SATADD
rrrrr!0,000110,RRRRR:I:::satadd
"satadd r<reg1>, r<reg2>"
// SATSUBI
rrrrr!0,110011,RRRRR + iiiiiiiiiiiiiiii:VI:::satsubi
-"satsubi <imm16>, r<reg1>, r<reg2>"
+"satsubi <simm16>, r<reg1>, r<reg2>"
{
COMPAT_2 (OP_660 ());
}
// SETF
rrrrr,1111110,cccc + 0000000000000000:IX:::setf
-"setf <cccc>, r<reg2>"
+"setf %s<cccc>, r<reg2>"
{
COMPAT_2 (OP_7E0 ());
}
COMPAT_2 (OP_7C0 ());
}
-// start-sanitize-v850e
rrrrr,111111,RRRRR + 0000000011100000:IX:::set1
*v850e
-// start-sanitize-v850eq
-*v850eq
-// end-sanitize-v850eq
+*v850ea
"set1 r<reg2>, [r<reg1>]"
{
COMPAT_2 (OP_E007E0 ());
-// end-sanitize-v850e
// SHL
rrrrr,111111,RRRRR + 0000000011000000:IX:::shl
"shl r<reg1>, r<reg2>"
// SLD
rrrrr,0110,ddddddd:IV:::sld.b
+"sld.bu <disp7>[ep], r<reg2>":(PSW & PSW_US)
"sld.b <disp7>[ep], r<reg2>"
{
- COMPAT_1 (OP_300 ());
+ unsigned32 addr = EP + disp7;
+ unsigned32 result = load_mem (addr, 1);
+ if (PSW & PSW_US)
+ {
+ GR[reg2] = result;
+ TRACE_LD_NAME ("sld.bu", addr, result);
+ }
+ else
+ {
+ result = EXTEND8 (result);
+ GR[reg2] = result;
+ TRACE_LD (addr, result);
+ }
}
rrrrr,1000,ddddddd:IV:::sld.h
+"sld.hu <disp8>[ep], r<reg2>":(PSW & PSW_US)
"sld.h <disp8>[ep], r<reg2>"
{
- COMPAT_1 (OP_400 ());
+ unsigned32 addr = EP + disp8;
+ unsigned32 result = load_mem (addr, 2);
+ if (PSW & PSW_US)
+ {
+ GR[reg2] = result;
+ TRACE_LD_NAME ("sld.hu", addr, result);
+ }
+ else
+ {
+ result = EXTEND16 (result);
+ GR[reg2] = result;
+ TRACE_LD (addr, result);
+ }
}
rrrrr,1010,dddddd,0:IV:::sld.w
"sld.w <disp8>[ep], r<reg2>"
{
- COMPAT_1 (OP_500 ());
+ unsigned32 addr = EP + disp8;
+ unsigned32 result = load_mem (addr, 4);
+ GR[reg2] = result;
+ TRACE_LD (addr, result);
}
-// start-sanitize-v850e
rrrrr!0,0000110,dddd:IV:::sld.bu
+*v850e
+*v850ea
+"sld.b <disp4>[ep], r<reg2>":(PSW & PSW_US)
"sld.bu <disp4>[ep], r<reg2>"
{
- unsigned long result;
-
- SAVE_1;
- result = load_mem (State.regs[30] + disp4, 1);
-
- /* start-sanitize-v850eq */
- if (PSW & PSW_US) {
- trace_input ("sld.b", OP_LOAD16, 1);
-
- State.regs[ reg2 ] = EXTEND8 (result);
- } else {
- /* end-sanitize-v850eq */
- trace_input ("sld.bu", OP_LOAD16, 1);
- State.regs[ reg2 ] = result;
- /* start-sanitize-v850eq */
- }
- /* end-sanitize-v850eq */
- trace_output (OP_LOAD16);
+ unsigned32 addr = EP + disp4;
+ unsigned32 result = load_mem (addr, 1);
+ if (PSW & PSW_US)
+ {
+ result = EXTEND8 (result);
+ GR[reg2] = result;
+ TRACE_LD_NAME ("sld.b", addr, result);
+ }
+ else
+ {
+ GR[reg2] = result;
+ TRACE_LD (addr, result);
+ }
}
-// end-sanitize-v850e
-// start-sanitize-v850e
rrrrr!0,0000111,dddd:IV:::sld.hu
+*v850e
+*v850ea
+"sld.h <disp5>[ep], r<reg2>":(PSW & PSW_US)
"sld.hu <disp5>[ep], r<reg2>"
{
- COMPAT_1 (OP_70 ());
+ unsigned32 addr = EP + disp5;
+ unsigned32 result = load_mem (addr, 2);
+ if (PSW & PSW_US)
+ {
+ result = EXTEND16 (result);
+ GR[reg2] = result;
+ TRACE_LD_NAME ("sld.h", addr, result);
+ }
+ else
+ {
+ GR[reg2] = result;
+ TRACE_LD (addr, result);
+ }
}
-// end-sanitize-v850e
-
// SST
rrrrr,0111,ddddddd:IV:::sst.b
// STSR
-//rrrrr,111111,RRRRR + 0000000001000000:IX:::stsr
-//"stsr r<regID>, r<reg2>"
-//{
-// COMPAT_2 (OP_4007E0 ());
-//}
-rrrrr,111111,RRRRR + 0000000001000000:IX:::stsr
-"stsr r<regID>, r<reg1>"
+rrrrr,111111,regID + 0000000001000000:IX:::stsr
+"stsr s<regID>, r<reg2>"
{
- SAVE_2;
-
- trace_input ("stsr", OP_STSR, 0);
-
- State.regs[ reg1 ] = State.sregs[ regID ];
-
- trace_output (OP_STSR);
+ TRACE_ALU_INPUT1 (SR[regID]);
+ GR[reg2] = SR[regID];
+ TRACE_ALU_RESULT (GR[reg2]);
}
-// start-sanitize-v850e
// SWITCH
00000000010,RRRRR:I:::switch
*v850e
-// start-sanitize-v850eq
-*v850eq
-// end-sanitize-v850eq
+*v850ea
"switch r<reg1>"
{
- COMPAT_1 (OP_40 ());
+ unsigned long adr;
+ SAVE_1;
+ trace_input ("switch", OP_REG, 0);
+ adr = (cia + 2) + (State.regs[ reg1 ] << 1);
+ nia = (cia + 2) + (EXTEND16 (load_mem (adr, 2)) << 1);
+ trace_output (OP_REG);
}
-// end-sanitize-v850e
-
-// start-sanitize-v850e
// SXB
00000000101,RRRRR:I:::sxb
*v850e
-// start-sanitize-v850eq
-*v850eq
-// end-sanitize-v850eq
+*v850ea
"sxb r<reg1>"
{
- COMPAT_1 (OP_A0 ());
+ TRACE_ALU_INPUT1 (GR[reg1]);
+ GR[reg1] = EXTEND8 (GR[reg1]);
+ TRACE_ALU_RESULT (GR[reg1]);
}
-
-
-// end-sanitize-v850e
-// start-sanitize-v850e
// SXH
00000000111,RRRRR:I:::sxh
*v850e
-// start-sanitize-v850eq
-*v850eq
-// end-sanitize-v850eq
+*v850ea
"sxh r<reg1>"
{
- COMPAT_1 (OP_E0 ());
+ TRACE_ALU_INPUT1 (GR[reg1]);
+ GR[reg1] = EXTEND16 (GR[reg1]);
+ TRACE_ALU_RESULT (GR[reg1]);
}
-// end-sanitize-v850e
// TRAP
00000111111,iiiii + 0000000100000000:X:::trap
"trap <vector>"
COMPAT_2 (OP_C7C0 ());
}
-// start-sanitize-v850e
rrrrr,111111,RRRRR + 0000000011100110:IX:::tst1
*v850e
-// start-sanitize-v850eq
-*v850eq
-// end-sanitize-v850eq
+*v850ea
"tst1 r<reg2>, [r<reg1>]"
{
COMPAT_2 (OP_E607E0 ());
-// end-sanitize-v850e
// XOR
rrrrr,001001,RRRRR:I:::xor
"xor r<reg1>, r<reg2>"
// XORI
rrrrr,110101,RRRRR + iiiiiiiiiiiiiiii:VI:::xori
-"xori <imm16>, r<reg1>, r<reg2>"
+"xori <uimm16>, r<reg1>, r<reg2>"
{
COMPAT_2 (OP_6A0 ());
}
-// start-sanitize-v850e
// ZXB
00000000100,RRRRR:I:::zxb
*v850e
-// start-sanitize-v850eq
-*v850eq
-// end-sanitize-v850eq
+*v850ea
"zxb r<reg1>"
{
- SAVE_1;
-
- trace_input ("zxb", OP_REG, 0);
-
- State.regs[ OP[0] ] &= 0xff;
-
- trace_output (OP_REG);
+ TRACE_ALU_INPUT1 (GR[reg1]);
+ GR[reg1] = GR[reg1] & 0xff;
+ TRACE_ALU_RESULT (GR[reg1]);
}
-
-
-// end-sanitize-v850e
-// start-sanitize-v850e
// ZXH
00000000110,RRRRR:I:::zxh
*v850e
-// start-sanitize-v850eq
-*v850eq
-// end-sanitize-v850eq
+*v850ea
"zxh r<reg1>"
{
- SAVE_1;
-
- trace_input ("zxh", OP_REG, 0);
-
- State.regs[ OP[0] ] &= 0xffff;
-
- trace_output (OP_REG);
+ TRACE_ALU_INPUT1 (GR[reg1]);
+ GR[reg1] = GR[reg1] & 0xffff;
+ TRACE_ALU_RESULT (GR[reg1]);
}
-
-// end-sanitize-v850e
-// Special - breakpoint - illegal
-// Hopefully, in the future, this instruction will go away
-1111111111111111 + 1111111111111111:Z:::breakpoint
-*v850
-{
- sim_engine_halt (SD, CPU, NULL, cia, sim_stopped, SIGTRAP);
-}
-
-// start-sanitize-v850e
-// First field could be any nonzero value.
+// Right field must be zero so that it doesn't clash with DIVH
+// Left field must be non-zero so that it doesn't clash with SWITCH
11111,000010,00000:I:::break
{
- sim_engine_halt (SD, CPU, NULL, cia, sim_stopped, SIGTRAP);
+ sim_engine_halt (SD, CPU, NULL, cia, sim_stopped, SIM_SIGTRAP);
}
-// end-sanitize-v850e
+// New breakpoint: 0x7E0 0x7E0
+00000,111111,00000 + 00000,11111,100000:X:::ilgop
+{
+ sim_engine_halt (SD, CPU, NULL, cia, sim_stopped, SIM_SIGTRAP);
+}
-// start-sanitize-v850eq
// DIVHN
rrrrr,111111,RRRRR + wwwww,01010,iiii,00:XI:::divhn
-*v850eq
+*v850ea
"divhn <imm5>, r<reg1>, r<reg2>, r<reg3>"
{
signed32 quotient;
// DIVHUN
rrrrr,111111,RRRRR + wwwww,01010,iiii,10:XI:::divhun
-*v850eq
+*v850ea
"divhun <imm5>, r<reg1>, r<reg2>, r<reg3>"
{
signed32 quotient;
// DIVN
rrrrr,111111,RRRRR + wwwww,01011,iiii,00:XI:::divn
-*v850eq
+*v850ea
"divn <imm5>, r<reg1>, r<reg2>, r<reg3>"
{
signed32 quotient;
// DIVUN
rrrrr,111111,RRRRR + wwwww,01011,iiii,10:XI:::divun
-*v850eq
+*v850ea
"divun <imm5>, r<reg1>, r<reg2>, r<reg3>"
{
signed32 quotient;
// SDIVHN
rrrrr,111111,RRRRR + wwwww,00110,iiii,00:XI:::sdivhn
-*v850eq
+*v850ea
"sdivhn <imm5>, r<reg1>, r<reg2>, r<reg3>"
{
COMPAT_2 (OP_18007E0 ());
// SDIVHUN
rrrrr,111111,RRRRR + wwwww,00110,iiii,10:XI:::sdivhun
-*v850eq
+*v850ea
"sdivhun <imm5>, r<reg1>, r<reg2>, r<reg3>"
{
COMPAT_2 (OP_18207E0 ());
// SDIVN
rrrrr,111111,RRRRR + wwwww,00111,iiii,00:XI:::sdivn
-*v850eq
+*v850ea
"sdivn <imm5>, r<reg1>, r<reg2>, r<reg3>"
{
COMPAT_2 (OP_1C007E0 ());
// SDIVUN
rrrrr,111111,RRRRR + wwwww,00111,iiii,10:XI:::sdivun
-*v850eq
+*v850ea
"sdivun <imm5>, r<reg1>, r<reg2>, r<reg3>"
{
COMPAT_2 (OP_1C207E0 ());
// PUSHML
000001111110,LLLL + LLLLLLLLLLLL,S,001:XIV:::pushml
-*v850eq
+*v850ea
"pushml <list18>"
{
int i;
// PUSHHML
000001111110,LLLL + LLLLLLLLLLLL,S,011:XIV:::pushmh
-*v850eq
+*v850ea
"pushhml <list18>"
{
COMPAT_2 (OP_307E0 ());
// POPML
000001111111,LLLL + LLLLLLLLLLLL,S,001:XIV:::popml
-*v850eq
+*v850ea
"popml <list18>"
{
COMPAT_2 (OP_107F0 ());
// POPMH
000001111111,LLLL + LLLLLLLLLLLL,S,011:XIV:::popmh
-*v850eq
+*v850ea
"popmh <list18>"
{
COMPAT_2 (OP_307F0 ());
}
-
-// end-sanitize-v850eq
projects / platform / upstream / binutils.git / blobdiff