-#include <signal.h>
#include "sim-main.h"
#include "v850_sim.h"
#include "simops.h"
+#include <sys/types.h>
+
#ifdef HAVE_UTIME_H
#include <utime.h>
#endif
#endif
#endif
+#include "targ-vals.h"
-
-
-
- /* FIXME - should be including a version of syscall.h that does not
- pollute the name space */
-#include "../../libgloss/v850/sys/syscall.h"
-
-#include "bfd.h"
#include "libiberty.h"
#include <errno.h>
#include <sys/time.h>
#endif
-/* start-sanitize-v850e */
-/* This is an array of the bit positions of registers r20 .. r31 in that order in a prepare/dispose instruction. */
-static int type1_regs[12] = { 27, 26, 25, 24, 31, 30, 29, 28, 23, 22, 0, 21 };
-/* end-sanitize-v850e */
-/* start-sanitize-v850eq */
-/* This is an array of the bit positions of registers r16 .. r31 in that order in a push/pop instruction. */
-static int type2_regs[16] = { 3, 2, 1, 0, 27, 26, 25, 24, 31, 30, 29, 28, 23, 22, 20, 21};
-/* This is an array of the bit positions of registers r1 .. r15 in that order in a push/pop instruction. */
-static int type3_regs[15] = { 2, 1, 0, 27, 26, 25, 24, 31, 30, 29, 28, 23, 22, 20, 21};
-/* end-sanitize-v850eq */
+/* This is an array of the bit positions of registers r20 .. r31 in
+ that order in a prepare/dispose instruction. */
+int type1_regs[12] = { 27, 26, 25, 24, 31, 30, 29, 28, 23, 22, 0, 21 };
+/* This is an array of the bit positions of registers r16 .. r31 in
+ that order in a push/pop instruction. */
+int type2_regs[16] = { 3, 2, 1, 0, 27, 26, 25, 24, 31, 30, 29, 28, 23, 22, 20, 21};
+/* This is an array of the bit positions of registers r1 .. r15 in
+ that order in a push/pop instruction. */
+int type3_regs[15] = { 2, 1, 0, 27, 26, 25, 24, 31, 30, 29, 28, 23, 22, 20, 21};
#ifdef DEBUG
#ifndef SIZE_INSTRUCTION
-#define SIZE_INSTRUCTION 6
-#endif
-
-#ifndef SIZE_OPERANDS
-#define SIZE_OPERANDS 16
+#define SIZE_INSTRUCTION 18
#endif
#ifndef SIZE_VALUES
#define SIZE_VALUES 11
#endif
-#ifndef SIZE_LOCATION
-#define SIZE_LOCATION 40
-#endif
+
+unsigned32 trace_values[3];
+int trace_num_values;
+unsigned32 trace_pc;
+const char *trace_name;
+int trace_module;
void
enum op_types type;
int size;
{
- char buf[1024];
- char *p;
- uint32 values[3];
- int num_values, i;
- const char *filename;
- const char *functionname;
- unsigned int linenumber;
if (!TRACE_ALU_P (STATE_CPU (simulator, 0)))
return;
- buf[0] = '\0';
-
- if (STATE_TEXT_SECTION (simulator)
- && PC >= STATE_TEXT_START (simulator)
- && PC < STATE_TEXT_END (simulator))
- {
- filename = (const char *)0;
- functionname = (const char *)0;
- linenumber = 0;
- if (bfd_find_nearest_line (STATE_PROG_BFD (simulator),
- STATE_TEXT_SECTION (simulator),
- (struct symbol_cache_entry **)0,
- PC - STATE_TEXT_START (simulator),
- &filename, &functionname, &linenumber))
- {
- p = buf;
- if (linenumber)
- {
- sprintf (p, "Line %5d ", linenumber);
- p += strlen (p);
- }
-
- if (functionname)
- {
- sprintf (p, "Func %s ", functionname);
- p += strlen (p);
- }
- else if (filename)
- {
- char *q = (char *) strrchr (filename, '/');
- sprintf (p, "File %s ", (q) ? q+1 : filename);
- p += strlen (p);
- }
-
- if (*p == ' ')
- *p = '\0';
- }
- }
-
- trace_printf (simulator, STATE_CPU (simulator, 0),
- "0x%.8x: %-*.*s %-*s",
- (unsigned)PC,
- SIZE_LOCATION, SIZE_LOCATION, buf,
- SIZE_INSTRUCTION, name);
+ trace_pc = PC;
+ trace_name = name;
+ trace_module = TRACE_ALU_IDX;
switch (type)
{
case OP_UNKNOWN:
case OP_NONE:
case OP_TRAP:
- num_values = 0;
+ trace_num_values = 0;
break;
case OP_REG:
case OP_REG_REG_MOVE:
- values[0] = State.regs[OP[0]];
- num_values = 1;
+ trace_values[0] = State.regs[OP[0]];
+ trace_num_values = 1;
break;
- /* start-sanitize-v850e */
case OP_BIT_CHANGE:
- /* end-sanitize-v850e */
case OP_REG_REG:
case OP_REG_REG_CMP:
- values[0] = State.regs[OP[1]];
- values[1] = State.regs[OP[0]];
- num_values = 2;
+ trace_values[0] = State.regs[OP[1]];
+ trace_values[1] = State.regs[OP[0]];
+ trace_num_values = 2;
break;
case OP_IMM_REG:
case OP_IMM_REG_CMP:
- values[0] = SEXT5 (OP[0]);
- values[1] = OP[1];
- num_values = 2;
+ trace_values[0] = SEXT5 (OP[0]);
+ trace_values[1] = OP[1];
+ trace_num_values = 2;
break;
case OP_IMM_REG_MOVE:
- values[0] = SEXT5 (OP[0]);
- num_values = 1;
+ trace_values[0] = SEXT5 (OP[0]);
+ trace_num_values = 1;
break;
case OP_COND_BR:
- values[0] = State.pc;
- values[1] = SEXT9 (OP[0]);
- values[2] = PSW;
- num_values = 3;
+ trace_values[0] = State.pc;
+ trace_values[1] = SEXT9 (OP[0]);
+ trace_values[2] = PSW;
+ trace_num_values = 3;
break;
case OP_LOAD16:
- values[0] = OP[1] * size;
- values[1] = State.regs[30];
- num_values = 2;
+ trace_values[0] = OP[1] * size;
+ trace_values[1] = State.regs[30];
+ trace_num_values = 2;
break;
case OP_STORE16:
- values[0] = State.regs[OP[0]];
- values[1] = OP[1] * size;
- values[2] = State.regs[30];
- num_values = 3;
+ trace_values[0] = State.regs[OP[0]];
+ trace_values[1] = OP[1] * size;
+ trace_values[2] = State.regs[30];
+ trace_num_values = 3;
break;
case OP_LOAD32:
- values[0] = EXTEND16 (OP[2]);
- values[1] = State.regs[OP[0]];
- num_values = 2;
+ trace_values[0] = EXTEND16 (OP[2]);
+ trace_values[1] = State.regs[OP[0]];
+ trace_num_values = 2;
break;
case OP_STORE32:
- values[0] = State.regs[OP[1]];
- values[1] = EXTEND16 (OP[2]);
- values[2] = State.regs[OP[0]];
- num_values = 3;
+ trace_values[0] = State.regs[OP[1]];
+ trace_values[1] = EXTEND16 (OP[2]);
+ trace_values[2] = State.regs[OP[0]];
+ trace_num_values = 3;
break;
case OP_JUMP:
- values[0] = SEXT22 (OP[0]);
- values[1] = State.pc;
- num_values = 2;
+ trace_values[0] = SEXT22 (OP[0]);
+ trace_values[1] = State.pc;
+ trace_num_values = 2;
break;
case OP_IMM_REG_REG:
- values[0] = EXTEND16 (OP[0]) << size;
- values[1] = State.regs[OP[1]];
- num_values = 2;
+ trace_values[0] = EXTEND16 (OP[0]) << size;
+ trace_values[1] = State.regs[OP[1]];
+ trace_num_values = 2;
+ break;
+
+ case OP_IMM16_REG_REG:
+ trace_values[0] = EXTEND16 (OP[2]) << size;
+ trace_values[1] = State.regs[OP[1]];
+ trace_num_values = 2;
break;
case OP_UIMM_REG_REG:
- values[0] = (OP[0] & 0xffff) << size;
- values[1] = State.regs[OP[1]];
- num_values = 2;
+ trace_values[0] = (OP[0] & 0xffff) << size;
+ trace_values[1] = State.regs[OP[1]];
+ trace_num_values = 2;
+ break;
+
+ case OP_UIMM16_REG_REG:
+ trace_values[0] = (OP[2]) << size;
+ trace_values[1] = State.regs[OP[1]];
+ trace_num_values = 2;
break;
case OP_BIT:
- num_values = 0;
+ trace_num_values = 0;
break;
case OP_EX1:
- values[0] = PSW;
- num_values = 1;
+ trace_values[0] = PSW;
+ trace_num_values = 1;
break;
case OP_EX2:
- num_values = 0;
+ trace_num_values = 0;
break;
case OP_LDSR:
- values[0] = State.regs[OP[0]];
- num_values = 1;
+ trace_values[0] = State.regs[OP[0]];
+ trace_num_values = 1;
break;
case OP_STSR:
- values[0] = State.sregs[OP[1]];
- num_values = 1;
+ trace_values[0] = State.sregs[OP[1]];
+ trace_num_values = 1;
}
- for (i = 0; i < num_values; i++)
- trace_printf (simulator, STATE_CPU (simulator, 0),
- "%*s0x%.8lx", SIZE_VALUES - 10, "", values[i]);
-
- while (i++ < 3)
- trace_printf (simulator, STATE_CPU (simulator, 0),
- "%*s", SIZE_VALUES, "");
}
void
-trace_output (result)
- enum op_types result;
+trace_result (int has_result, unsigned32 result)
{
- if (TRACE_ALU_P (STATE_CPU (simulator, 0)))
- {
- switch (result)
- {
- default:
- case OP_UNKNOWN:
- case OP_NONE:
- case OP_TRAP:
- case OP_REG:
- case OP_REG_REG_CMP:
- case OP_IMM_REG_CMP:
- case OP_COND_BR:
- case OP_STORE16:
- case OP_STORE32:
- case OP_BIT:
- case OP_EX2:
- break;
-
- case OP_LOAD16:
- case OP_STSR:
- trace_printf (simulator, STATE_CPU (simulator, 0),
- " :: 0x%.8lx", (unsigned long)State.regs[OP[0]]);
- break;
+ char buf[1000];
+ char *chp;
- case OP_REG_REG:
- case OP_REG_REG_MOVE:
- case OP_IMM_REG:
- case OP_IMM_REG_MOVE:
- case OP_LOAD32:
- case OP_EX1:
- trace_printf (simulator, STATE_CPU (simulator, 0),
- " :: 0x%.8lx", (unsigned long)State.regs[OP[1]]);
- break;
+ buf[0] = '\0';
+ chp = buf;
- case OP_IMM_REG_REG:
- case OP_UIMM_REG_REG:
- trace_printf (simulator, STATE_CPU (simulator, 0),
- " :: 0x%.8lx", (unsigned long)State.regs[OP[2]]);
- break;
+ /* write out the values saved during the trace_input call */
+ {
+ int i;
+ for (i = 0; i < trace_num_values; i++)
+ {
+ sprintf (chp, "%*s0x%.8lx", SIZE_VALUES - 10, "",
+ (long) trace_values[i]);
+ chp = strchr (chp, '\0');
+ }
+ while (i++ < 3)
+ {
+ sprintf (chp, "%*s", SIZE_VALUES, "");
+ chp = strchr (chp, '\0');
+ }
+ }
- case OP_JUMP:
- if (OP[1] != 0)
- trace_printf (simulator, STATE_CPU (simulator, 0),
- " :: 0x%.8lx", (unsigned long)State.regs[OP[1]]);
- break;
+ /* append any result to the end of the buffer */
+ if (has_result)
+ sprintf (chp, " :: 0x%.8lx", (unsigned long)result);
+
+ trace_generic (simulator, STATE_CPU (simulator, 0), trace_module, buf);
+}
- case OP_LDSR:
- trace_printf (simulator, STATE_CPU (simulator, 0),
- " :: 0x%.8lx", (unsigned long)State.sregs[OP[1]]);
- break;
- }
+void
+trace_output (result)
+ enum op_types result;
+{
+ if (!TRACE_ALU_P (STATE_CPU (simulator, 0)))
+ return;
- trace_printf (simulator, STATE_CPU (simulator, 0),
- "\n");
+ switch (result)
+ {
+ default:
+ case OP_UNKNOWN:
+ case OP_NONE:
+ case OP_TRAP:
+ case OP_REG:
+ case OP_REG_REG_CMP:
+ case OP_IMM_REG_CMP:
+ case OP_COND_BR:
+ case OP_STORE16:
+ case OP_STORE32:
+ case OP_BIT:
+ case OP_EX2:
+ trace_result (0, 0);
+ break;
+
+ case OP_LOAD16:
+ case OP_STSR:
+ trace_result (1, State.regs[OP[0]]);
+ break;
+
+ case OP_REG_REG:
+ case OP_REG_REG_MOVE:
+ case OP_IMM_REG:
+ case OP_IMM_REG_MOVE:
+ case OP_LOAD32:
+ case OP_EX1:
+ trace_result (1, State.regs[OP[1]]);
+ break;
+
+ case OP_IMM_REG_REG:
+ case OP_UIMM_REG_REG:
+ case OP_IMM16_REG_REG:
+ case OP_UIMM16_REG_REG:
+ trace_result (1, State.regs[OP[1]]);
+ break;
+
+ case OP_JUMP:
+ if (OP[1] != 0)
+ trace_result (1, State.regs[OP[1]]);
+ else
+ trace_result (0, 0);
+ break;
+
+ case OP_LDSR:
+ trace_result (1, State.sregs[OP[1]]);
+ break;
}
}
-
#endif
\f
/* Returns 1 if the specific condition is met, returns 0 otherwise. */
-static unsigned int
+int
condition_met (unsigned code)
{
unsigned int psw = PSW;
return 1;
}
-/* start-sanitize-v850e */
static unsigned long
Add32 (unsigned long a1, unsigned long a2, int * carry)
}
static void
-Multiply64 (boolean sign, unsigned long op0)
+Multiply64 (int sign, unsigned long op0)
{
unsigned long op1;
unsigned long lo;
RdLo += 1;
}
- State.regs[ OP[1] ] = RdLo;
- State.regs[ OP[2] >> 11 ] = RdHi;
+ /* Don't store into register 0. */
+ if (OP[1])
+ State.regs[ OP[1] ] = RdLo;
+ if (OP[2] >> 11)
+ State.regs[ OP[2] >> 11 ] = RdHi;
return;
}
-/* end-sanitize-v850e */
\f
/* Read a null terminated string from memory, return in a buffer */
static char *
char *buf;
int nr = 0;
while (sim_core_read_1 (STATE_CPU (sd, 0),
- PC, sim_core_read_map, addr + nr) != 0)
+ PC, read_map, addr + nr) != 0)
nr++;
buf = NZALLOC (char, nr + 1);
sim_read (simulator, addr, buf, nr);
while (1)
{
unsigned32 a = sim_core_read_4 (STATE_CPU (sd, 0),
- PC, sim_core_read_map, addr + nr * 4);
+ PC, read_map, addr + nr * 4);
if (a == 0) break;
buf[nr] = fetch_str (sd, a);
nr ++;
}
\f
-/* sld.b */
-int
-OP_300 ()
-{
- unsigned long result;
-
- result = load_mem (State.regs[30] + (OP[3] & 0x7f), 1);
-
-/* start-sanitize-v850eq */
-#ifdef ARCH_v850eq
- trace_input ("sld.bu", OP_LOAD16, 1);
-
- State.regs[ OP[1] ] = result;
-#else
-/* end-sanitize-v850eq */
- trace_input ("sld.b", OP_LOAD16, 1);
-
- State.regs[ OP[1] ] = EXTEND8 (result);
-/* start-sanitize-v850eq */
-#endif
-/* end-sanitize-v850eq */
-
- trace_output (OP_LOAD16);
-
- return 2;
-}
-
-/* sld.h */
-int
-OP_400 ()
-{
- unsigned long result;
-
- result = load_mem (State.regs[30] + ((OP[3] & 0x7f) << 1), 2);
-
-/* start-sanitize-v850eq */
-#ifdef ARCH_v850eq
- trace_input ("sld.hu", OP_LOAD16, 2);
-
- State.regs[ OP[1] ] = result;
-#else
-/* end-sanitize-v850eq */
- trace_input ("sld.h", OP_LOAD16, 2);
-
- State.regs[ OP[1] ] = EXTEND16 (result);
-/* start-sanitize-v850eq */
-#endif
-/* end-sanitize-v850eq */
-
- trace_output (OP_LOAD16);
-
- return 2;
-}
-
-/* sld.w */
-int
-OP_500 ()
-{
- trace_input ("sld.w", OP_LOAD16, 4);
-
- State.regs[ OP[1] ] = load_mem (State.regs[30] + ((OP[3] & 0x7f) << 1), 4);
-
- trace_output (OP_LOAD16);
-
- return 2;
-}
-
/* sst.b */
int
OP_380 ()
return 4;
}
-static int
-branch (int code)
-{
- trace_input ("Bcond", OP_COND_BR, 0);
- trace_output (OP_COND_BR);
-
- if (condition_met (code))
- return SEXT9 (((OP[3] & 0x70) >> 3) | ((OP[3] & 0xf800) >> 7));
- else
- return 2;
-}
-
-/* bv disp9 */
-int
-OP_580 ()
-{
- return branch (0);
-}
-
-/* bl disp9 */
-int
-OP_581 ()
-{
- return branch (1);
-}
-
-/* be disp9 */
-int
-OP_582 ()
-{
- return branch (2);
-}
-
-/* bnh disp 9*/
-int
-OP_583 ()
-{
- return branch (3);
-}
-
-/* bn disp9 */
-int
-OP_584 ()
-{
- return branch (4);
-}
-
-/* br disp9 */
-int
-OP_585 ()
-{
- return branch (5);
-}
-
-/* blt disp9 */
-int
-OP_586 ()
-{
- return branch (6);
-}
-
-/* ble disp9 */
-int
-OP_587 ()
-{
- return branch (7);
-}
-
-/* bnv disp9 */
-int
-OP_588 ()
-{
- return branch (8);
-}
-
-/* bnl disp9 */
-int
-OP_589 ()
-{
- return branch (9);
-}
-
-/* bne disp9 */
-int
-OP_58A ()
-{
- return branch (10);
-}
-
-/* bh disp9 */
-int
-OP_58B ()
-{
- return branch (11);
-}
-
-/* bp disp9 */
-int
-OP_58C ()
-{
- return branch (12);
-}
-
-/* bsa disp9 */
-int
-OP_58D ()
-{
- return branch (13);
-}
-
-/* bge disp9 */
-int
-OP_58E ()
-{
- return branch (14);
-}
-
-/* bgt disp9 */
-int
-OP_58F ()
-{
- return branch (15);
-}
-
-/* jarl/jr disp22, reg */
-int
-OP_780 ()
-{
- trace_input ("jarl/jr", OP_JUMP, 0);
-
- if (OP[ 1 ] != 0)
- State.regs[ OP[1] ] = PC + 4;
-
- trace_output (OP_JUMP);
-
- return SEXT22 (((OP[3] & 0x3f) << 16) | OP[2]);
-}
-
/* add reg, reg */
int
OP_1C0 ()
{
unsigned int op0, op1, result, z, s, cy, ov;
- trace_input ("addi", OP_IMM_REG_REG, 0);
+ trace_input ("addi", OP_IMM16_REG_REG, 0);
/* Compute the result. */
PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
| (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
- trace_output (OP_IMM_REG_REG);
+ trace_output (OP_IMM16_REG_REG);
return 4;
}
}
/* sxh reg1 */
-/* mulh reg1, reg2 */
int
OP_E0 ()
{
-/* start-sanitize-v850e */
- if (OP[1] == 0)
- {
- trace_input ("sxh", OP_REG, 0);
+ trace_input ("mulh", OP_REG_REG, 0);
- State.regs[ OP[0] ] = EXTEND16 (State.regs[ OP[0] ]);
-
- trace_output (OP_REG);
- }
- else
-/* end-sanitize-v850e */
- {
- trace_input ("mulh", OP_REG_REG, 0);
+ State.regs[ OP[1] ] = (EXTEND16 (State.regs[ OP[1] ]) * EXTEND16 (State.regs[ OP[0] ]));
- State.regs[ OP[1] ] = (EXTEND16 (State.regs[ OP[1] ]) * EXTEND16 (State.regs[ OP[0] ]));
-
- trace_output (OP_REG_REG);
- }
+ trace_output (OP_REG_REG);
return 2;
}
int
OP_6E0 ()
{
- if (OP[1] == 0)
- {
- }
- else
- {
- trace_input ("mulhi", OP_IMM_REG_REG, 0);
+ trace_input ("mulhi", OP_IMM16_REG_REG, 0);
- State.regs[ OP[1] ] = EXTEND16 (State.regs[ OP[0] ]) * EXTEND16 (OP[2]);
+ State.regs[ OP[1] ] = EXTEND16 (State.regs[ OP[0] ]) * EXTEND16 (OP[2]);
- trace_output (OP_IMM_REG_REG);
- }
+ trace_output (OP_IMM16_REG_REG);
return 4;
}
-/* divh reg1, reg2 */
-/* switch reg1 */
-int
-OP_40 ()
-{
-/* start-sanitize-v850e */
- if (OP[1] == 0)
- {
- unsigned long adr;
-
- trace_input ("switch", OP_REG, 0);
-
- adr = State.pc + 2 + (State.regs[ OP[0] ] << 1);
- State.pc = State.pc + 2 + (EXTEND16 (load_mem (adr, 2)) << 1);
-
- trace_output (OP_REG);
- }
- else
-/* end-sanitize-v850e */
- {
- unsigned int op0, op1, result, ov, s, z;
- int temp;
-
- trace_input ("divh", OP_REG_REG, 0);
-
- /* Compute the result. */
- temp = EXTEND16 (State.regs[ OP[0] ]);
- op0 = temp;
- op1 = State.regs[OP[1]];
-
- if (op0 == 0xffffffff && op1 == 0x80000000)
- {
- result = 0x80000000;
- ov = 1;
- }
- else if (op0 != 0)
- {
- result = op1 / op0;
- ov = 0;
- }
- else
- {
- result = 0x0;
- ov = 1;
- }
-
- /* Compute the condition codes. */
- z = (result == 0);
- s = (result & 0x80000000);
-
- /* Store the result and condition codes. */
- State.regs[OP[1]] = result;
- PSW &= ~(PSW_Z | PSW_S | PSW_OV);
- PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
- | (ov ? PSW_OV : 0));
- trace_output (OP_REG_REG);
- }
-
- return 2;
-}
-
/* cmp reg, reg */
int
OP_1E0 ()
return 4;
}
-/* zxh reg1 */
/* satadd reg,reg */
int
OP_C0 ()
{
-/* start-sanitize-v850e */
- if (OP[1] == 0)
+ unsigned int op0, op1, result, z, s, cy, ov, sat;
+
+ trace_input ("satadd", OP_REG_REG, 0);
+ /* Compute the result. */
+ op0 = State.regs[ OP[0] ];
+ op1 = State.regs[ OP[1] ];
+ result = op0 + op1;
+
+ /* Compute the condition codes. */
+ z = (result == 0);
+ s = (result & 0x80000000);
+ cy = (result < op0 || result < op1);
+ ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
+ && (op0 & 0x80000000) != (result & 0x80000000));
+ sat = ov;
+
+ /* Handle saturated results. */
+ if (sat && s)
{
- trace_input ("zxh", OP_REG, 0);
-
- State.regs[ OP[0] ] &= 0xffff;
-
- trace_output (OP_REG);
+ /* An overflow that results in a negative result implies that we
+ became too positive. */
+ result = 0x7fffffff;
+ s = 0;
}
- else
-/* end-sanitize-v850e */
+ else if (sat)
{
- unsigned int op0, op1, result, z, s, cy, ov, sat;
-
- trace_input ("satadd", OP_REG_REG, 0);
- /* Compute the result. */
- op0 = State.regs[ OP[0] ];
- op1 = State.regs[ OP[1] ];
- result = op0 + op1;
-
- /* Compute the condition codes. */
- z = (result == 0);
- s = (result & 0x80000000);
- cy = (result < op0 || result < op1);
- ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
- && (op0 & 0x80000000) != (result & 0x80000000));
- sat = ov;
-
- /* Store the result and condition codes. */
- State.regs[OP[1]] = result;
- PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
- PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
- | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
- | (sat ? PSW_SAT : 0));
-
- /* Handle saturated results. */
- if (sat && s)
- State.regs[OP[1]] = 0x80000000;
- else if (sat)
- State.regs[OP[1]] = 0x7fffffff;
- trace_output (OP_REG_REG);
+ /* Any other overflow must have thus been too negative. */
+ result = 0x80000000;
+ s = 1;
+ z = 0;
}
+ /* Store the result and condition codes. */
+ State.regs[OP[1]] = result;
+ PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
+ PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
+ | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
+ | (sat ? PSW_SAT : 0));
+
+ trace_output (OP_REG_REG);
+
return 2;
}
&& (op0 & 0x80000000) != (result & 0x80000000));
sat = ov;
+ /* Handle saturated results. */
+ if (sat && s)
+ {
+ /* An overflow that results in a negative result implies that we
+ became too positive. */
+ result = 0x7fffffff;
+ s = 0;
+ }
+ else if (sat)
+ {
+ /* Any other overflow must have thus been too negative. */
+ result = 0x80000000;
+ s = 1;
+ z = 0;
+ }
+
/* Store the result and condition codes. */
State.regs[OP[1]] = result;
PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
| (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
| (sat ? PSW_SAT : 0));
-
- /* Handle saturated results. */
- if (sat && s)
- State.regs[OP[1]] = 0x80000000;
- else if (sat)
- State.regs[OP[1]] = 0x7fffffff;
trace_output (OP_IMM_REG);
return 2;
}
/* satsub reg1, reg2 */
-/* sxb reg1 */
int
OP_A0 ()
{
-/* start-sanitize-v850e */
- if (OP[1] == 0)
- {
- trace_input ("sxb", OP_REG, 0);
-
- State.regs[ OP[0] ] = EXTEND8 (State.regs[ OP[0] ]);
+ unsigned int op0, op1, result, z, s, cy, ov, sat;
+
+ trace_input ("satsub", OP_REG_REG, 0);
+
+ /* Compute the result. */
+ op0 = State.regs[ OP[0] ];
+ op1 = State.regs[ OP[1] ];
+ result = op1 - op0;
+
+ /* Compute the condition codes. */
+ z = (result == 0);
+ s = (result & 0x80000000);
+ cy = (op1 < op0);
+ ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
+ && (op1 & 0x80000000) != (result & 0x80000000));
+ sat = ov;
- trace_output (OP_REG);
+ /* Handle saturated results. */
+ if (sat && s)
+ {
+ /* An overflow that results in a negative result implies that we
+ became too positive. */
+ result = 0x7fffffff;
+ s = 0;
}
- else
-/* end-sanitize-v850e */
+ else if (sat)
{
- unsigned int op0, op1, result, z, s, cy, ov, sat;
-
- trace_input ("satsub", OP_REG_REG, 0);
-
- /* Compute the result. */
- op0 = State.regs[ OP[0] ];
- op1 = State.regs[ OP[1] ];
- result = op1 - op0;
-
- /* Compute the condition codes. */
- z = (result == 0);
- s = (result & 0x80000000);
- cy = (op1 < op0);
- ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
- && (op1 & 0x80000000) != (result & 0x80000000));
- sat = ov;
-
- /* Store the result and condition codes. */
- State.regs[OP[1]] = result;
- PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
- PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
- | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
- | (sat ? PSW_SAT : 0));
-
- /* Handle saturated results. */
- if (sat && s)
- State.regs[OP[1]] = 0x80000000;
- else if (sat)
- State.regs[OP[1]] = 0x7fffffff;
- trace_output (OP_REG_REG);
+ /* Any other overflow must have thus been too negative. */
+ result = 0x80000000;
+ s = 1;
+ z = 0;
}
+ /* Store the result and condition codes. */
+ State.regs[OP[1]] = result;
+ PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
+ PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
+ | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
+ | (sat ? PSW_SAT : 0));
+
+ trace_output (OP_REG_REG);
return 2;
}
&& (op1 & 0x80000000) != (result & 0x80000000));
sat = ov;
+ /* Handle saturated results. */
+ if (sat && s)
+ {
+ /* An overflow that results in a negative result implies that we
+ became too positive. */
+ result = 0x7fffffff;
+ s = 0;
+ }
+ else if (sat)
+ {
+ /* Any other overflow must have thus been too negative. */
+ result = 0x80000000;
+ s = 1;
+ z = 0;
+ }
+
/* Store the result and condition codes. */
State.regs[OP[1]] = result;
PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
| (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
| (sat ? PSW_SAT : 0));
- /* Handle saturated results. */
- if (sat && s)
- State.regs[OP[1]] = 0x80000000;
- else if (sat)
- State.regs[OP[1]] = 0x7fffffff;
trace_output (OP_IMM_REG);
return 4;
}
/* satsubr reg,reg */
-/* zxb reg1 */
int
OP_80 ()
{
-/* start-sanitize-v850e */
- if (OP[1] == 0)
- {
- trace_input ("zxb", OP_REG, 0);
-
- State.regs[ OP[0] ] &= 0xff;
+ unsigned int op0, op1, result, z, s, cy, ov, sat;
+
+ trace_input ("satsubr", OP_REG_REG, 0);
+
+ /* Compute the result. */
+ op0 = State.regs[ OP[0] ];
+ op1 = State.regs[ OP[1] ];
+ result = op0 - op1;
+
+ /* Compute the condition codes. */
+ z = (result == 0);
+ s = (result & 0x80000000);
+ cy = (op0 < op1);
+ ov = ((op0 & 0x80000000) != (op1 & 0x80000000)
+ && (op0 & 0x80000000) != (result & 0x80000000));
+ sat = ov;
- trace_output (OP_REG);
+ /* Handle saturated results. */
+ if (sat && s)
+ {
+ /* An overflow that results in a negative result implies that we
+ became too positive. */
+ result = 0x7fffffff;
+ s = 0;
}
- else
-/* end-sanitize-v850e */
+ else if (sat)
{
- unsigned int op0, op1, result, z, s, cy, ov, sat;
-
- trace_input ("satsubr", OP_REG_REG, 0);
-
- /* Compute the result. */
- op0 = State.regs[ OP[0] ];
- op1 = State.regs[ OP[1] ];
- result = op0 - op1;
-
- /* Compute the condition codes. */
- z = (result == 0);
- s = (result & 0x80000000);
- cy = (result < op0);
- ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
- && (op1 & 0x80000000) != (result & 0x80000000));
- sat = ov;
-
- /* Store the result and condition codes. */
- State.regs[OP[1]] = result;
- PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
- PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
- | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
- | (sat ? PSW_SAT : 0));
-
- /* Handle saturated results. */
- if (sat && s)
- State.regs[OP[1]] = 0x80000000;
- else if (sat)
- State.regs[OP[1]] = 0x7fffffff;
- trace_output (OP_REG_REG);
+ /* Any other overflow must have thus been too negative. */
+ result = 0x80000000;
+ s = 1;
+ z = 0;
}
+
+ /* Store the result and condition codes. */
+ State.regs[OP[1]] = result;
+ PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
+ PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
+ | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
+ | (sat ? PSW_SAT : 0));
+
+ trace_output (OP_REG_REG);
return 2;
}
return 2;
}
-/* mov reg, reg */
-int
-OP_0 ()
-{
- trace_input ("mov", OP_REG_REG_MOVE, 0);
-
- State.regs[ OP[1] ] = State.regs[ OP[0] ];
-
- trace_output (OP_REG_REG_MOVE);
-
- return 2;
-}
-
/* mov sign_extend(imm5), reg */
-/* callt imm6 */
int
OP_200 ()
{
-/* start-sanitize-v850e */
- if (OP[1] == 0)
- {
- unsigned long adr;
-
- trace_input ("callt", OP_LOAD16, 1);
-
- CTPC = PC + 2;
- CTPSW = PSW;
-
- adr = CTBP + ((OP[3] & 0x3f) << 1);
-
- PC = CTBP + load_mem (adr, 1);
-
- trace_output (OP_LOAD16);
-
- return 0;
- }
- else
-/* end-sanitize-v850e */
- {
- int value = SEXT5 (OP[0]);
-
- trace_input ("mov", OP_IMM_REG_MOVE, 0);
-
- State.regs[ OP[1] ] = value;
-
- trace_output (OP_IMM_REG_MOVE);
-
- return 2;
- }
-}
-
-/* mov imm32, reg1 */
-/* movea sign_extend(imm16), reg, reg */
-int
-OP_620 ()
-{
-/* start-sanitize-v850e */
- if (OP[1] == 0)
- {
- trace_input ("mov", OP_IMM_REG, 4);
-
- State.regs[ OP[0] ] = load_mem (PC + 2, 4);
-
- trace_output (OP_IMM_REG);
-
- return 6;
- }
- else
-/* end-sanitize-v850e */
- {
- trace_input ("movea", OP_IMM_REG_REG, 0);
+ int value = SEXT5 (OP[0]);
- State.regs[ OP[1] ] = State.regs[ OP[0] ] + EXTEND16 (OP[2]);
+ trace_input ("mov", OP_IMM_REG_MOVE, 0);
- trace_output (OP_IMM_REG_REG);
-
- return 4;
- }
+ State.regs[ OP[1] ] = value;
+
+ trace_output (OP_IMM_REG_MOVE);
+
+ return 2;
}
-/* dispose imm5, list12 [, reg1] */
/* movhi imm16, reg, reg */
int
OP_640 ()
{
-/* start-sanitize-v850e */
-
- if (OP[1] == 0)
- {
- int i;
+ trace_input ("movhi", OP_UIMM16_REG_REG, 16);
- trace_input ("dispose", OP_PUSHPOP1, 0);
-
- SP += (OP[3] & 0x3e) << 1;
-
- /* Load the registers with lower number registers being retrieved from higher addresses. */
- for (i = 12; i--;)
- if ((OP[3] & (1 << type1_regs[ i ])))
- {
- State.regs[ 20 + i ] = load_mem (SP, 4);
- SP += 4;
- }
-
- if ((OP[3] & 0x1f0000) != 0)
- {
- PC = State.regs[ (OP[3] >> 16) & 0x1f];
- return 0;
- }
+ State.regs[ OP[1] ] = State.regs[ OP[0] ] + (OP[2] << 16);
- trace_output (OP_PUSHPOP1);
- }
- else
-/* end-sanitize-v850e */
- {
- trace_input ("movhi", OP_UIMM_REG_REG, 16);
-
- State.regs[ OP[1] ] = State.regs[ OP[0] ] + (OP[2] << 16);
-
- trace_output (OP_UIMM_REG_REG);
- }
+ trace_output (OP_UIMM16_REG_REG);
return 4;
}
/* Compute the condition codes. */
z = (result == 0);
s = (result & 0x80000000);
- cy = (op1 & (1 << (op0 - 1)));
+ cy = op0 ? (op1 & (1 << (op0 - 1))) : 0;
/* Store the result and condition codes. */
State.regs[ OP[1] ] = result;
/* Compute the condition codes. */
z = (result == 0);
s = (result & 0x80000000);
- cy = (op1 & (1 << (op0 - 1)));
+ cy = op0 ? (op1 & (1 << (op0 - 1))) : 0;
/* Store the result and condition codes. */
State.regs[OP[1]] = result;
/* Compute the condition codes. */
z = (result == 0);
s = (result & 0x80000000);
- cy = (op1 & (1 << (32 - op0)));
+ cy = op0 ? (op1 & (1 << (32 - op0))) : 0;
/* Store the result and condition codes. */
State.regs[OP[1]] = result;
/* Compute the condition codes. */
z = (result == 0);
s = (result & 0x80000000);
- cy = (op1 & (1 << (32 - op0)));
+ cy = op0 ? (op1 & (1 << (32 - op0))) : 0;
/* Store the result and condition codes. */
State.regs[OP[1]] = result;
/* Compute the condition codes. */
z = (result == 0);
s = (result & 0x80000000);
- cy = (op1 & (1 << (op0 - 1)));
+ cy = op0 ? (op1 & (1 << (op0 - 1))) : 0;
/* Store the result and condition codes. */
State.regs[OP[1]] = result;
/* Compute the condition codes. */
z = (result == 0);
s = (result & 0x80000000);
- cy = (op1 & (1 << (op0 - 1)));
+ cy = op0 ? (op1 & (1 << (op0 - 1))) : 0;
/* Store the result and condition codes. */
State.regs[OP[1]] = result;
{
unsigned int op0, op1, result, z, s;
- trace_input ("ori", OP_UIMM_REG_REG, 0);
+ trace_input ("ori", OP_UIMM16_REG_REG, 0);
op0 = OP[2];
op1 = State.regs[ OP[0] ];
result = op0 | op1;
State.regs[OP[1]] = result;
PSW &= ~(PSW_Z | PSW_S | PSW_OV);
PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
- trace_output (OP_UIMM_REG_REG);
+ trace_output (OP_UIMM16_REG_REG);
return 4;
}
{
unsigned int result, z;
- trace_input ("andi", OP_UIMM_REG_REG, 0);
+ trace_input ("andi", OP_UIMM16_REG_REG, 0);
result = OP[2] & State.regs[ OP[0] ];
PSW &= ~(PSW_Z | PSW_S | PSW_OV);
PSW |= (z ? PSW_Z : 0);
- trace_output (OP_UIMM_REG_REG);
+ trace_output (OP_UIMM16_REG_REG);
return 4;
}
{
unsigned int op0, op1, result, z, s;
- trace_input ("xori", OP_UIMM_REG_REG, 0);
+ trace_input ("xori", OP_UIMM16_REG_REG, 0);
op0 = OP[2];
op1 = State.regs[ OP[0] ];
result = op0 ^ op1;
State.regs[OP[1]] = result;
PSW &= ~(PSW_Z | PSW_S | PSW_OV);
PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
- trace_output (OP_UIMM_REG_REG);
+ trace_output (OP_UIMM16_REG_REG);
return 4;
}
return 4;
}
-/* breakpoint */
-int
-OP_FFFF ()
-{
- sim_engine_halt (simulator, STATE_CPU (simulator, 0), NULL, PC,
- sim_stopped, SIGTRAP);
- return 0;
-}
-
/* di */
int
OP_16007E0 ()
/* FIXME this should put processor into a mode where NMI still handled */
trace_output (OP_NONE);
sim_engine_halt (simulator, STATE_CPU (simulator, 0), NULL, PC,
- sim_stopped, SIGTRAP);
- return 0;
-}
-
-/* reti */
-int
-OP_14007E0 ()
-{
- trace_input ("reti", OP_NONE, 0);
- trace_output (OP_NONE);
-
- /* Restore for NMI if only NP on, otherwise is interrupt or exception. */
- if ((PSW & (PSW_NP | PSW_EP)) == PSW_NP)
- {
- PC = FEPC - 4;
- PSW = FEPSW;
- }
- else
- {
- PC = EIPC - 4;
- PSW = EIPSW;
- }
-
+ sim_stopped, SIM_SIGTRAP);
return 0;
}
#define MEMPTR(x) (map (x))
+ RETERR = 0;
+
switch (FUNC)
{
#ifdef HAVE_FORK
-#ifdef SYS_fork
- case SYS_fork:
+#ifdef TARGET_SYS_fork
+ case TARGET_SYS_fork:
RETVAL = fork ();
+ RETERR = errno;
break;
#endif
#endif
#ifdef HAVE_EXECVE
-#ifdef SYS_execv
- case SYS_execve:
+#ifdef TARGET_SYS_execv
+ case TARGET_SYS_execve:
{
char *path = fetch_str (simulator, PARM1);
char **argv = fetch_argv (simulator, PARM2);
char **envp = fetch_argv (simulator, PARM3);
RETVAL = execve (path, argv, envp);
- zfree (path);
+ free (path);
freeargv (argv);
freeargv (envp);
+ RETERR = errno;
break;
}
#endif
#endif
#if HAVE_EXECV
-#ifdef SYS_execv
- case SYS_execv:
+#ifdef TARGET_SYS_execv
+ case TARGET_SYS_execv:
{
char *path = fetch_str (simulator, PARM1);
char **argv = fetch_argv (simulator, PARM2);
RETVAL = execv (path, argv);
- zfree (path);
+ free (path);
freeargv (argv);
+ RETERR = errno;
break;
}
#endif
#endif
#if 0
-#ifdef SYS_pipe
- case SYS_pipe:
+#ifdef TARGET_SYS_pipe
+ case TARGET_SYS_pipe:
{
reg_t buf;
int host_fd[2];
SW (buf, host_fd[0]);
buf += sizeof(uint16);
SW (buf, host_fd[1]);
+ RETERR = errno;
}
break;
#endif
#endif
#if 0
-#ifdef SYS_wait
- case SYS_wait:
+#ifdef TARGET_SYS_wait
+ case TARGET_SYS_wait:
{
int status;
RETVAL = wait (&status);
SW (PARM1, status);
+ RETERR = errno;
}
break;
#endif
#endif
-#ifdef SYS_read
- case SYS_read:
+#ifdef TARGET_SYS_read
+ case TARGET_SYS_read:
{
char *buf = zalloc (PARM3);
RETVAL = sim_io_read (simulator, PARM1, buf, PARM3);
sim_write (simulator, PARM2, buf, PARM3);
- zfree (buf);
+ free (buf);
+ if ((int) RETVAL < 0)
+ RETERR = sim_io_get_errno (simulator);
break;
}
#endif
-#ifdef SYS_write
- case SYS_write:
+#ifdef TARGET_SYS_write
+ case TARGET_SYS_write:
{
char *buf = zalloc (PARM3);
sim_read (simulator, PARM2, buf, PARM3);
RETVAL = sim_io_write_stdout (simulator, buf, PARM3);
else
RETVAL = sim_io_write (simulator, PARM1, buf, PARM3);
- zfree (buf);
+ free (buf);
+ if ((int) RETVAL < 0)
+ RETERR = sim_io_get_errno (simulator);
break;
}
#endif
-#ifdef SYS_lseek
- case SYS_lseek:
+#ifdef TARGET_SYS_lseek
+ case TARGET_SYS_lseek:
RETVAL = sim_io_lseek (simulator, PARM1, PARM2, PARM3);
+ if ((int) RETVAL < 0)
+ RETERR = sim_io_get_errno (simulator);
break;
#endif
-#ifdef SYS_close
- case SYS_close:
+#ifdef TARGET_SYS_close
+ case TARGET_SYS_close:
RETVAL = sim_io_close (simulator, PARM1);
+ if ((int) RETVAL < 0)
+ RETERR = sim_io_get_errno (simulator);
break;
#endif
-#ifdef SYS_open
- case SYS_open:
+#ifdef TARGET_SYS_open
+ case TARGET_SYS_open:
{
char *buf = fetch_str (simulator, PARM1);
RETVAL = sim_io_open (simulator, buf, PARM2);
- zfree (buf);
+ free (buf);
+ if ((int) RETVAL < 0)
+ RETERR = sim_io_get_errno (simulator);
break;
}
#endif
-#ifdef SYS_exit
- case SYS_exit:
+#ifdef TARGET_SYS_exit
+ case TARGET_SYS_exit:
if ((PARM1 & 0xffff0000) == 0xdead0000 && (PARM1 & 0xffff) != 0)
/* get signal encoded by kill */
sim_engine_halt (simulator, STATE_CPU (simulator, 0), NULL, PC,
else if (PARM1 == 0xdead)
/* old libraries */
sim_engine_halt (simulator, STATE_CPU (simulator, 0), NULL, PC,
- sim_exited, SIGABRT);
+ sim_stopped, SIM_SIGABRT);
else
/* PARM1 has exit status */
sim_engine_halt (simulator, STATE_CPU (simulator, 0), NULL, PC,
break;
#endif
-#if !defined(__GO32__) && !defined(_WIN32)
-#ifdef SYS_stat
- case SYS_stat: /* added at hmsi */
+#ifdef TARGET_SYS_stat
+ case TARGET_SYS_stat: /* added at hmsi */
/* stat system call */
{
struct stat host_stat;
reg_t buf;
char *path = fetch_str (simulator, PARM1);
- RETVAL = stat (path, &host_stat);
+ RETVAL = sim_io_stat (simulator, path, &host_stat);
+
+ free (path);
+ buf = PARM2;
+
+ /* Just wild-assed guesses. */
+ store_mem (buf, 2, host_stat.st_dev);
+ store_mem (buf + 2, 2, host_stat.st_ino);
+ store_mem (buf + 4, 4, host_stat.st_mode);
+ store_mem (buf + 8, 2, host_stat.st_nlink);
+ store_mem (buf + 10, 2, host_stat.st_uid);
+ store_mem (buf + 12, 2, host_stat.st_gid);
+ store_mem (buf + 14, 2, host_stat.st_rdev);
+ store_mem (buf + 16, 4, host_stat.st_size);
+ store_mem (buf + 20, 4, host_stat.st_atime);
+ store_mem (buf + 28, 4, host_stat.st_mtime);
+ store_mem (buf + 36, 4, host_stat.st_ctime);
+
+ if ((int) RETVAL < 0)
+ RETERR = sim_io_get_errno (simulator);
+ }
+ break;
+#endif
+
+#ifdef TARGET_SYS_fstat
+ case TARGET_SYS_fstat:
+ /* fstat system call */
+ {
+ struct stat host_stat;
+ reg_t buf;
+
+ RETVAL = sim_io_fstat (simulator, PARM1, &host_stat);
- zfree (path);
buf = PARM2;
/* Just wild-assed guesses. */
store_mem (buf + 20, 4, host_stat.st_atime);
store_mem (buf + 28, 4, host_stat.st_mtime);
store_mem (buf + 36, 4, host_stat.st_ctime);
+
+ if ((int) RETVAL < 0)
+ RETERR = sim_io_get_errno (simulator);
+ }
+ break;
+#endif
+
+#ifdef TARGET_SYS_rename
+ case TARGET_SYS_rename:
+ {
+ char *oldpath = fetch_str (simulator, PARM1);
+ char *newpath = fetch_str (simulator, PARM2);
+ RETVAL = sim_io_rename (simulator, oldpath, newpath);
+ free (oldpath);
+ free (newpath);
+ if ((int) RETVAL < 0)
+ RETERR = sim_io_get_errno (simulator);
}
break;
#endif
+
+#ifdef TARGET_SYS_unlink
+ case TARGET_SYS_unlink:
+ {
+ char *path = fetch_str (simulator, PARM1);
+ RETVAL = sim_io_unlink (simulator, path);
+ free (path);
+ if ((int) RETVAL < 0)
+ RETERR = sim_io_get_errno (simulator);
+ }
+ break;
#endif
#ifdef HAVE_CHOWN
-#ifdef SYS_chown
- case SYS_chown:
+#ifdef TARGET_SYS_chown
+ case TARGET_SYS_chown:
{
char *path = fetch_str (simulator, PARM1);
RETVAL = chown (path, PARM2, PARM3);
- zfree (path);
+ free (path);
+ RETERR = errno;
}
break;
#endif
#endif
#if HAVE_CHMOD
-#ifdef SYS_chmod
- case SYS_chmod:
+#ifdef TARGET_SYS_chmod
+ case TARGET_SYS_chmod:
{
char *path = fetch_str (simulator, PARM1);
RETVAL = chmod (path, PARM2);
- zfree (path);
+ free (path);
+ RETERR = errno;
}
break;
#endif
#endif
-#ifdef SYS_time
+#ifdef TARGET_SYS_time
#if HAVE_TIME
- case SYS_time:
+ case TARGET_SYS_time:
{
time_t now;
RETVAL = time (&now);
store_mem (PARM1, 4, now);
+ RETERR = errno;
}
break;
#endif
#endif
#if !defined(__GO32__) && !defined(_WIN32)
-#ifdef SYS_times
- case SYS_times:
+#ifdef TARGET_SYS_times
+ case TARGET_SYS_times:
{
struct tms tms;
RETVAL = times (&tms);
store_mem (PARM1 + 4, 4, tms.tms_stime);
store_mem (PARM1 + 8, 4, tms.tms_cutime);
store_mem (PARM1 + 12, 4, tms.tms_cstime);
+ reterr = errno;
break;
}
#endif
#endif
-#ifdef SYS_gettimeofday
+#ifdef TARGET_SYS_gettimeofday
#if !defined(__GO32__) && !defined(_WIN32)
- case SYS_gettimeofday:
+ case TARGET_SYS_gettimeofday:
{
struct timeval t;
struct timezone tz;
store_mem (PARM1 + 4, 4, t.tv_usec);
store_mem (PARM2, 4, tz.tz_minuteswest);
store_mem (PARM2 + 4, 4, tz.tz_dsttime);
+ RETERR = errno;
break;
}
#endif
#endif
-#ifdef SYS_utime
+#ifdef TARGET_SYS_utime
#if HAVE_UTIME
- case SYS_utime:
+ case TARGET_SYS_utime:
{
/* Cast the second argument to void *, to avoid type mismatch
if a prototype is present. */
default:
abort ();
}
- RETERR = errno;
errno = save_errno;
return 4;
ECR |= 0x40 + OP[0];
/* Flag that we are now doing exception processing. */
PSW |= PSW_EP | PSW_ID;
- PC = ((OP[0] < 0x10) ? 0x40 : 0x50) - 4;
+ PC = (OP[0] < 0x10) ? 0x40 : 0x50;
return 0;
}
}
-/* ldsr, reg,reg */
-int
-OP_2007E0 ()
-{
- trace_input ("ldsr", OP_LDSR, 0);
-
- State.sregs[ OP[1] ] = State.regs[ OP[0] ];
-
- trace_output (OP_LDSR);
-
- return 4;
-}
-
-/* stsr */
-int
-OP_4007E0 ()
-{
- trace_input ("stsr", OP_STSR, 0);
-
- State.regs[ OP[1] ] = State.sregs[ OP[0] ];
-
- trace_output (OP_STSR);
-
- return 4;
-}
-
-/* start-sanitize-v850e */
/* tst1 reg2, [reg1] */
int
OP_E607E0 (void)
temp = load_mem (State.regs[ OP[0] ], 1);
PSW &= ~PSW_Z;
- if ((temp & (1 << State.regs[ OP[1] & 0x7 ])) == 0)
+ if ((temp & (1 << (State.regs[ OP[1] ] & 0x7))) == 0)
PSW |= PSW_Z;
trace_output (OP_BIT);
return 4;
}
-/* end-sanitize-v850e */
-/* start-sanitize-v850e */
/* mulu reg1, reg2, reg3 */
int
OP_22207E0 (void)
{
trace_input ("mulu", OP_REG_REG_REG, 0);
- Multiply64 (false, State.regs[ OP[0] ]);
+ Multiply64 (0, State.regs[ OP[0] ]);
trace_output (OP_REG_REG_REG);
return 4;
}
-/* end-sanitize-v850e */
-/* start-sanitize-v850e */
-
#define BIT_CHANGE_OP( name, binop ) \
unsigned int bit; \
unsigned int temp; \
\
trace_input (name, OP_BIT_CHANGE, 0); \
\
- bit = 1 << State.regs[ OP[1] & 0x7 ]; \
+ bit = 1 << (State.regs[ OP[1] ] & 0x7); \
temp = load_mem (State.regs[ OP[0] ], 1); \
\
PSW &= ~PSW_Z; \
return 4;
}
-/* end-sanitize-v850e */
-/* start-sanitize-v850eq */
-/* This function is courtesy of Sugimoto at NEC, via Seow Tan (Soew_Tan@el.nec.com) */
-static void
+
+/* This function is courtesy of Sugimoto at NEC, via Seow Tan
+ (Soew_Tan@el.nec.com) */
+void
divun
(
unsigned int N,
unsigned long int als,
unsigned long int sfi,
- unsigned long int * quotient_ptr,
- unsigned long int * remainder_ptr,
- boolean * overflow_ptr
+ unsigned32 /*unsigned long int*/ * quotient_ptr,
+ unsigned32 /*unsigned long int*/ * remainder_ptr,
+ int * overflow_ptr
)
{
unsigned long ald = sfi >> (N - 1);
}
/* This function is courtesy of Sugimoto at NEC, via Seow Tan (Soew_Tan@el.nec.com) */
-static void
+void
divn
(
unsigned int N,
unsigned long int als,
unsigned long int sfi,
- signed long int * quotient_ptr,
- signed long int * remainder_ptr,
- boolean * overflow_ptr
+ signed32 /*signed long int*/ * quotient_ptr,
+ signed32 /*signed long int*/ * remainder_ptr,
+ int * overflow_ptr
)
{
unsigned long ald = (signed long) sfi >> (N - 1);
int
OP_1C207E0 (void)
{
- unsigned long int quotient;
- unsigned long int remainder;
+ unsigned32 /*unsigned long int*/ quotient;
+ unsigned32 /*unsigned long int*/ remainder;
unsigned long int divide_by;
unsigned long int divide_this;
- boolean overflow = false;
+ int overflow = 0;
unsigned int imm5;
trace_input ("sdivun", OP_IMM_REG_REG_REG, 0);
int
OP_1C007E0 (void)
{
- signed long int quotient;
- signed long int remainder;
+ signed32 /*signed long int*/ quotient;
+ signed32 /*signed long int*/ remainder;
signed long int divide_by;
signed long int divide_this;
- boolean overflow = false;
+ int overflow = 0;
unsigned int imm5;
trace_input ("sdivn", OP_IMM_REG_REG_REG, 0);
imm5 = 32 - ((OP[3] & 0x3c0000) >> 17);
- divide_by = State.regs[ OP[0] ];
- divide_this = State.regs[ OP[1] ] << imm5;
+ divide_by = (signed32) State.regs[ OP[0] ];
+ divide_this = (signed32) (State.regs[ OP[1] ] << imm5);
divn (imm5, divide_by, divide_this, & quotient, & remainder, & overflow);
int
OP_18207E0 (void)
{
- unsigned long int quotient;
- unsigned long int remainder;
+ unsigned32 /*unsigned long int*/ quotient;
+ unsigned32 /*unsigned long int*/ remainder;
unsigned long int divide_by;
unsigned long int divide_this;
- boolean overflow = false;
+ int overflow = 0;
unsigned int imm5;
trace_input ("sdivhun", OP_IMM_REG_REG_REG, 0);
int
OP_18007E0 (void)
{
- signed long int quotient;
- signed long int remainder;
+ signed32 /*signed long int*/ quotient;
+ signed32 /*signed long int*/ remainder;
signed long int divide_by;
signed long int divide_this;
- boolean overflow = false;
+ int overflow = 0;
unsigned int imm5;
trace_input ("sdivhn", OP_IMM_REG_REG_REG, 0);
imm5 = 32 - ((OP[3] & 0x3c0000) >> 17);
divide_by = EXTEND16 (State.regs[ OP[0] ]);
- divide_this = State.regs[ OP[1] ] << imm5;
+ divide_this = (signed32) (State.regs[ OP[1] ] << imm5);
divn (imm5, divide_by, divide_this, & quotient, & remainder, & overflow);
return 4;
}
-/* end-sanitize-v850eq */
-/* start-sanitize-v850e */
/* divu reg1, reg2, reg3 */
int
OP_2C207E0 (void)
unsigned long int remainder;
unsigned long int divide_by;
unsigned long int divide_this;
- boolean overflow = false;
+ int overflow = 0;
+
+ trace_input ("divu", OP_REG_REG_REG, 0);
- if ((OP[3] & 0x3c0000) == 0)
+ /* Compute the result. */
+
+ divide_by = State.regs[ OP[0] ];
+ divide_this = State.regs[ OP[1] ];
+
+ if (divide_by == 0)
{
- trace_input ("divu", OP_REG_REG_REG, 0);
-
- /* Compute the result. */
-
- divide_by = State.regs[ OP[0] ];
- divide_this = State.regs[ OP[1] ];
-
- if (divide_by == 0)
- {
- overflow = true;
- divide_by = 1;
- }
-
- State.regs[ OP[1] ] = quotient = divide_this / divide_by;
- State.regs[ OP[2] >> 11 ] = remainder = divide_this % divide_by;
-
- /* Set condition codes. */
- PSW &= ~(PSW_Z | PSW_S | PSW_OV);
-
- if (overflow) PSW |= PSW_OV;
- if (quotient == 0) PSW |= PSW_Z;
- if (quotient & 0x80000000) PSW |= PSW_S;
-
- trace_output (OP_REG_REG_REG);
+ PSW |= PSW_OV;
}
-/* start-sanitize-v850eq */
-/* divun imm5, reg1, reg2, reg3 */
else
{
- unsigned int imm5;
-
- trace_input ("divun", OP_IMM_REG_REG_REG, 0);
-
- imm5 = 32 - ((OP[3] & 0x3c0000) >> 17);
-
- divide_by = State.regs[ OP[0] ];
- divide_this = State.regs[ OP[1] ];
-
- divun (imm5, divide_by, divide_this, & quotient, & remainder, & overflow);
-
- State.regs[ OP[1] ] = quotient;
- State.regs[ OP[2] >> 11 ] = remainder;
-
+ State.regs[ OP[1] ] = quotient = divide_this / divide_by;
+ State.regs[ OP[2] >> 11 ] = remainder = divide_this % divide_by;
+
/* Set condition codes. */
PSW &= ~(PSW_Z | PSW_S | PSW_OV);
-
+
if (overflow) PSW |= PSW_OV;
if (quotient == 0) PSW |= PSW_Z;
if (quotient & 0x80000000) PSW |= PSW_S;
-
- trace_output (OP_IMM_REG_REG_REG);
}
-/* end-sanitize-v850eq */
+
+ trace_output (OP_REG_REG_REG);
return 4;
}
-/* end-sanitize-v850e */
-/* start-sanitize-v850e */
/* div reg1, reg2, reg3 */
int
OP_2C007E0 (void)
signed long int remainder;
signed long int divide_by;
signed long int divide_this;
- boolean overflow = false;
- if ((OP[3] & 0x3c0000) == 0)
+ trace_input ("div", OP_REG_REG_REG, 0);
+
+ /* Compute the result. */
+
+ divide_by = (signed32) State.regs[ OP[0] ];
+ divide_this = State.regs[ OP[1] ];
+
+ if (divide_by == 0)
{
- trace_input ("div", OP_REG_REG_REG, 0);
-
- /* Compute the result. */
-
- divide_by = State.regs[ OP[0] ];
- divide_this = State.regs[ OP[1] ];
-
- if (divide_by == 0 || (divide_by == -1 && divide_this == (1 << 31)))
- {
- overflow = true;
- divide_by = 1;
- }
-
- State.regs[ OP[1] ] = quotient = divide_this / divide_by;
- State.regs[ OP[2] >> 11 ] = remainder = divide_this % divide_by;
-
- /* Set condition codes. */
- PSW &= ~(PSW_Z | PSW_S | PSW_OV);
-
- if (overflow) PSW |= PSW_OV;
- if (quotient == 0) PSW |= PSW_Z;
- if (quotient < 0) PSW |= PSW_S;
-
- trace_output (OP_REG_REG_REG);
+ PSW |= PSW_OV;
+ }
+ else if (divide_by == -1 && divide_this == (1L << 31))
+ {
+ PSW &= ~PSW_Z;
+ PSW |= PSW_OV | PSW_S;
+ State.regs[ OP[1] ] = (1 << 31);
+ State.regs[ OP[2] >> 11 ] = 0;
}
-/* start-sanitize-v850eq */
-/* divn imm5, reg1, reg2, reg3 */
else
{
- unsigned int imm5;
-
- trace_input ("divn", OP_IMM_REG_REG_REG, 0);
-
- imm5 = 32 - ((OP[3] & 0x3c0000) >> 17);
-
- divide_by = State.regs[ OP[0] ];
- divide_this = State.regs[ OP[1] ];
-
- divn (imm5, divide_by, divide_this, & quotient, & remainder, & overflow);
-
- State.regs[ OP[1] ] = quotient;
- State.regs[ OP[2] >> 11 ] = remainder;
-
+ divide_this = (signed32) divide_this;
+ State.regs[ OP[1] ] = quotient = divide_this / divide_by;
+ State.regs[ OP[2] >> 11 ] = remainder = divide_this % divide_by;
+
/* Set condition codes. */
PSW &= ~(PSW_Z | PSW_S | PSW_OV);
-
- if (overflow) PSW |= PSW_OV;
+
if (quotient == 0) PSW |= PSW_Z;
if (quotient < 0) PSW |= PSW_S;
-
- trace_output (OP_IMM_REG_REG_REG);
}
-/* end-sanitize-v850eq */
+
+ trace_output (OP_REG_REG_REG);
return 4;
}
-/* end-sanitize-v850e */
-/* start-sanitize-v850e */
/* divhu reg1, reg2, reg3 */
int
OP_28207E0 (void)
unsigned long int remainder;
unsigned long int divide_by;
unsigned long int divide_this;
- boolean overflow = false;
+ int overflow = 0;
+
+ trace_input ("divhu", OP_REG_REG_REG, 0);
- if ((OP[3] & 0x3c0000) == 0)
+ /* Compute the result. */
+
+ divide_by = State.regs[ OP[0] ] & 0xffff;
+ divide_this = State.regs[ OP[1] ];
+
+ if (divide_by == 0)
{
- trace_input ("divhu", OP_REG_REG_REG, 0);
-
- /* Compute the result. */
-
- divide_by = State.regs[ OP[0] ] & 0xffff;
- divide_this = State.regs[ OP[1] ];
-
- if (divide_by == 0)
- {
- overflow = true;
- divide_by = 1;
- }
-
- State.regs[ OP[1] ] = quotient = divide_this / divide_by;
- State.regs[ OP[2] >> 11 ] = remainder = divide_this % divide_by;
-
- /* Set condition codes. */
- PSW &= ~(PSW_Z | PSW_S | PSW_OV);
-
- if (overflow) PSW |= PSW_OV;
- if (quotient == 0) PSW |= PSW_Z;
- if (quotient & 0x80000000) PSW |= PSW_S;
-
- trace_output (OP_REG_REG_REG);
+ PSW |= PSW_OV;
}
-/* start-sanitize-v850eq */
-/* divhun imm5, reg1, reg2, reg3 */
else
{
- unsigned int imm5;
-
- trace_input ("divhun", OP_IMM_REG_REG_REG, 0);
-
- imm5 = 32 - ((OP[3] & 0x3c0000) >> 17);
-
- divide_by = State.regs[ OP[0] ] & 0xffff;
- divide_this = State.regs[ OP[1] ];
-
- divun (imm5, divide_by, divide_this, & quotient, & remainder, & overflow);
-
- State.regs[ OP[1] ] = quotient;
- State.regs[ OP[2] >> 11 ] = remainder;
-
+ State.regs[ OP[1] ] = quotient = divide_this / divide_by;
+ State.regs[ OP[2] >> 11 ] = remainder = divide_this % divide_by;
+
/* Set condition codes. */
PSW &= ~(PSW_Z | PSW_S | PSW_OV);
-
+
if (overflow) PSW |= PSW_OV;
if (quotient == 0) PSW |= PSW_Z;
if (quotient & 0x80000000) PSW |= PSW_S;
-
- trace_output (OP_IMM_REG_REG_REG);
}
-/* end-sanitize-v850eq */
+
+ trace_output (OP_REG_REG_REG);
return 4;
}
-/* end-sanitize-v850e */
-/* start-sanitize-v850e */
/* divh reg1, reg2, reg3 */
int
OP_28007E0 (void)
signed long int remainder;
signed long int divide_by;
signed long int divide_this;
- boolean overflow = false;
+ int overflow = 0;
+
+ trace_input ("divh", OP_REG_REG_REG, 0);
+
+ /* Compute the result. */
- if ((OP[3] & 0x3c0000) == 0)
+ divide_by = EXTEND16 (State.regs[ OP[0] ]);
+ divide_this = State.regs[ OP[1] ];
+
+ if (divide_by == 0)
{
- trace_input ("divh", OP_REG_REG_REG, 0);
-
- /* Compute the result. */
-
- divide_by = State.regs[ OP[0] ];
- divide_this = EXTEND16 (State.regs[ OP[1] ]);
-
- if (divide_by == 0 || (divide_by == -1 && divide_this == (1 << 31)))
- {
- overflow = true;
- divide_by = 1;
- }
-
- State.regs[ OP[1] ] = quotient = divide_this / divide_by;
- State.regs[ OP[2] >> 11 ] = remainder = divide_this % divide_by;
-
- /* Set condition codes. */
- PSW &= ~(PSW_Z | PSW_S | PSW_OV);
-
- if (overflow) PSW |= PSW_OV;
- if (quotient == 0) PSW |= PSW_Z;
- if (quotient < 0) PSW |= PSW_S;
-
- trace_output (OP_REG_REG_REG);
+ PSW |= PSW_OV;
+ }
+ else if (divide_by == -1 && divide_this == (1L << 31))
+ {
+ PSW &= ~PSW_Z;
+ PSW |= PSW_OV | PSW_S;
+ State.regs[ OP[1] ] = (1 << 31);
+ State.regs[ OP[2] >> 11 ] = 0;
}
-/* start-sanitize-v850eq */
-/* divhn imm5, reg1, reg2, reg3 */
else
{
- unsigned int imm5;
-
- trace_input ("divhn", OP_IMM_REG_REG_REG, 0);
-
- imm5 = 32 - ((OP[3] & 0x3c0000) >> 17);
-
- divide_by = EXTEND16 (State.regs[ OP[0] ]);
- divide_this = State.regs[ OP[1] ];
-
- divn (imm5, divide_by, divide_this, & quotient, & remainder, & overflow);
-
- State.regs[ OP[1] ] = quotient;
- State.regs[ OP[2] >> 11 ] = remainder;
-
+ divide_this = (signed32) divide_this;
+ State.regs[ OP[1] ] = quotient = divide_this / divide_by;
+ State.regs[ OP[2] >> 11 ] = remainder = divide_this % divide_by;
+
/* Set condition codes. */
PSW &= ~(PSW_Z | PSW_S | PSW_OV);
-
- if (overflow) PSW |= PSW_OV;
+
if (quotient == 0) PSW |= PSW_Z;
if (quotient < 0) PSW |= PSW_S;
-
- trace_output (OP_IMM_REG_REG_REG);
}
-/* end-sanitize-v850eq */
+
+ trace_output (OP_REG_REG_REG);
return 4;
}
-/* end-sanitize-v850e */
-/* start-sanitize-v850e */
/* mulu imm9, reg2, reg3 */
int
OP_24207E0 (void)
{
trace_input ("mulu", OP_IMM_REG_REG, 0);
- Multiply64 (false, (OP[3] & 0x1f) | ((OP[3] >> 13) & 0x1e0));
+ Multiply64 (0, (OP[3] & 0x1f) | ((OP[3] >> 13) & 0x1e0));
trace_output (OP_IMM_REG_REG);
return 4;
}
-/* end-sanitize-v850e */
-/* start-sanitize-v850e */
/* mul imm9, reg2, reg3 */
int
OP_24007E0 (void)
{
trace_input ("mul", OP_IMM_REG_REG, 0);
- Multiply64 (true, (OP[3] & 0x1f) | ((OP[3] >> 13) & 0x1e0));
-
- trace_output (OP_IMM_REG_REG);
-
- return 4;
-}
-
-/* end-sanitize-v850e */
-/* start-sanitize-v850e */
-/* cmov imm5, reg2, reg3 */
-int
-OP_30007E0 (void)
-{
- trace_input ("cmov", OP_IMM_REG_REG, 0);
+ Multiply64 (1, SEXT9 ((OP[3] & 0x1f) | ((OP[3] >> 13) & 0x1e0)));
- State.regs[ OP[2] >> 11 ] = condition_met (OP[0]) ? SEXT5( OP[0] ) : State.regs[ OP[1] ];
-
trace_output (OP_IMM_REG_REG);
return 4;
-
-}
-
-/* end-sanitize-v850e */
-/* start-sanitize-v850e */
-/* ctret */
-int
-OP_14407E0 (void)
-{
- trace_input ("ctret", OP_NONE, 0);
-
- PC = CTPC;
- PSW = CTPSW;
-
- trace_output (OP_NONE);
-
- return 0;
-}
-
-/* end-sanitize-v850e */
-/* start-sanitize-v850e */
-/* hsw */
-int
-OP_34407E0 (void)
-{
- unsigned long value;
-
- trace_input ("hsw", OP_REG_REG3, 0);
-
- value = State.regs[ OP[ 1 ] ];
- value >>= 16;
- value |= (State.regs[ OP[ 1 ] ] << 16);
-
- State.regs[ OP[2] >> 11 ] = value;
-
- PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
-
- if (value == 0) PSW |= PSW_Z;
- if (value & 0x80000000) PSW |= PSW_S;
- if (((value & 0xffff) == 0) || (value & 0xffff0000) == 0) PSW |= PSW_CY;
-
- trace_output (OP_REG_REG3);
-
- return 4;
-}
-
-/* end-sanitize-v850e */
-/* start-sanitize-v850e */
-#define WORDHASNULLBYTE(x) (((x) - 0x01010101) & ~(x)&0x80808080)
-
-/* bsw */
-int
-OP_34007E0 (void)
-{
- unsigned long value;
-
- trace_input ("bsw", OP_REG_REG3, 0);
-
- value = State.regs[ OP[ 1 ] ];
- value >>= 24;
- value |= (State.regs[ OP[ 1 ] ] << 24);
- value |= ((State.regs[ OP[ 1 ] ] << 8) & 0x00ff0000);
- value |= ((State.regs[ OP[ 1 ] ] >> 8) & 0x0000ff00);
-
- State.regs[ OP[2] >> 11 ] = value;
-
- PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
-
- if (value == 0) PSW |= PSW_Z;
- if (value & 0x80000000) PSW |= PSW_S;
- if (WORDHASNULLBYTE (value)) PSW |= PSW_CY;
-
- trace_output (OP_REG_REG3);
-
- return 4;
-}
-
-/* end-sanitize-v850e */
-/* start-sanitize-v850e */
-/* bsh */
-int
-OP_34207E0 (void)
-{
- unsigned long value;
-
- trace_input ("bsh", OP_REG_REG3, 0);
-
- value = State.regs[ OP[ 1 ] ];
- value >>= 8;
- value |= ((State.regs[ OP[ 1 ] ] << 8) & 0xff00ff00);
- value |= ((State.regs[ OP[ 1 ] ] >> 8) & 0x000000ff);
-
- State.regs[ OP[2] >> 11 ] = value;
-
- PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
-
- if (value == 0) PSW |= PSW_Z;
- if (value & 0x80000000) PSW |= PSW_S;
- if (((value & 0xff) == 0) || (value & 0x00ff) == 0) PSW |= PSW_CY;
-
- trace_output (OP_REG_REG3);
-
- return 4;
}
-/* end-sanitize-v850e */
-/* start-sanitize-v850e */
-/* pushml list18 */
/* ld.hu */
int
OP_107E0 (void)
{
- if (OP[ 1 ] == 0)
- {
- int i;
-
- trace_input ("pushml", OP_PUSHPOP3, 0);
-
- /* Store the registers with lower number registers being placed at higher addresses. */
- for (i = 0; i < 15; i++)
- if ((OP[3] & (1 << type3_regs[ i ])))
- {
- SP -= 4;
- store_mem (SP & ~ 3, 4, State.regs[ i + 1 ]);
- }
-
- if (OP[3] & (1 << 3))
- {
- SP -= 4;
-
- store_mem (SP & ~ 3, 4, PSW);
- }
-
- if (OP[3] & (1 << 19))
- {
- SP -= 8;
-
- if ((PSW & PSW_NP) && ((PSW & PSW_EP) == 0))
- {
- store_mem ((SP + 4) & ~ 3, 4, FEPC);
- store_mem ( SP & ~ 3, 4, FEPSW);
- }
- else
- {
- store_mem ((SP + 4) & ~ 3, 4, EIPC);
- store_mem ( SP & ~ 3, 4, EIPSW);
- }
- }
-
- trace_output (OP_PUSHPOP2);
- }
- else
- {
- int adr;
+ int adr;
- trace_input ("ld.hu", OP_LOAD32, 2);
+ trace_input ("ld.hu", OP_LOAD32, 2);
- adr = State.regs[ OP[0] ] + EXTEND16 (OP[2] & ~1);
- adr &= ~0x1;
+ adr = State.regs[ OP[0] ] + EXTEND16 (OP[2] & ~1);
+ adr &= ~0x1;
- State.regs[ OP[1] ] = load_mem (adr, 2);
+ State.regs[ OP[1] ] = load_mem (adr, 2);
- trace_output (OP_LOAD32);
- }
+ trace_output (OP_LOAD32);
return 4;
}
-/* end-sanitize-v850e */
-/* start-sanitize-v850e */
-/* prepare list12, imm5 */
+
/* ld.bu */
int
OP_10780 (void)
{
- if (OP[ 1 ] == 0)
- {
- int i;
-
- trace_input ("prepare", OP_PUSHPOP1, 0);
-
- /* Store the registers with lower number registers being placed at higher addresses. */
- for (i = 0; i < 12; i++)
- if ((OP[3] & (1 << type1_regs[ i ])))
- {
- SP -= 4;
- store_mem (SP, 4, State.regs[ 20 + i ]);
- }
-
- SP -= (OP[3] & 0x3e) << 1;
-
- trace_output (OP_PUSHPOP1);
- }
- else
- {
- int adr;
+ int adr;
- trace_input ("ld.bu", OP_LOAD32, 1);
+ trace_input ("ld.bu", OP_LOAD32, 1);
- adr = (State.regs[ OP[0] ]
- + (EXTEND16 (OP[2] & ~1) | ((OP[3] >> 5) & 1)));
+ adr = (State.regs[ OP[0] ]
+ + (EXTEND16 (OP[2] & ~1) | ((OP[3] >> 5) & 1)));
- State.regs[ OP[1] ] = load_mem (adr, 1);
+ State.regs[ OP[1] ] = load_mem (adr, 1);
- trace_output (OP_LOAD32);
- }
+ trace_output (OP_LOAD32);
return 4;
}
return 4;
}
-/* end-sanitize-v850e */
-/* start-sanitize-v850e */
-/* sld.hu */
-int
-OP_70 (void)
-{
- unsigned long result;
-
- result = load_mem (State.regs[30] + ((OP[3] & 0xf) << 1), 2);
-
-/* start-sanitize-v850eq */
-#ifdef ARCH_v850eq
- trace_input ("sld.h", OP_LOAD16, 2);
-
- State.regs[ OP[1] ] = EXTEND16 (result);
-#else
-/* end-sanitize-v850eq */
- trace_input ("sld.hu", OP_LOAD16, 2);
-
- State.regs[ OP[1] ] = result;
-/* start-sanitize-v850eq */
-#endif
-/* end-sanitize-v850eq */
-
- trace_output (OP_LOAD16);
-
- return 2;
-}
-
-/* end-sanitize-v850e */
-/* start-sanitize-v850e */
-/* cmov reg1, reg2, reg3 */
-int
-OP_32007E0 (void)
-{
- trace_input ("cmov", OP_REG_REG_REG, 0);
-
- State.regs[ OP[2] >> 11 ] = condition_met (OP[0]) ? State.regs[ OP[0] ] : State.regs[ OP[1] ];
-
- trace_output (OP_REG_REG_REG);
-
- return 4;
-}
-
-/* end-sanitize-v850e */
-/* start-sanitize-v850e */
/* mul reg1, reg2, reg3 */
int
OP_22007E0 (void)
{
trace_input ("mul", OP_REG_REG_REG, 0);
- Multiply64 (true, State.regs[ OP[0] ]);
+ Multiply64 (1, State.regs[ OP[0] ]);
trace_output (OP_REG_REG_REG);
return 4;
}
-/* end-sanitize-v850e */
-/* start-sanitize-v850eq */
-
/* popmh list18 */
int
OP_307F0 (void)
return 4;
}
-/* end-sanitize-v850eq */
projects / external / binutils.git / blobdiff