-/* Simulator for Motorolla's MCore processor
- Copyright (C) 1999 Free Software Foundation, Inc.
+/* Simulator for Motorola's MCore processor
+ Copyright (C) 1999, 2000 Free Software Foundation, Inc.
Contributed by Cygnus Solutions.
This file is part of GDB, the GNU debugger.
#include <sys/param.h>
#include <netinet/in.h> /* for byte ordering macros */
#include "bfd.h"
-#include "callback.h"
+#include "gdb/callback.h"
#include "libiberty.h"
-#include "remote-sim.h"
+#include "gdb/remote-sim.h"
#ifndef NUM_ELEM
#define NUM_ELEM(A) (sizeof (A) / sizeof (A)[0])
typedef long int word;
typedef unsigned long int uword;
+static int target_big_endian = 0;
static unsigned long heap_ptr = 0;
host_callback * callback;
the least significant. */
retval = 0;
+ if (! target_big_endian)
+ {
+ for (p = endaddr; p > startaddr;)
+ retval = (retval << 8) | * -- p;
+ }
+ else
{
for (p = startaddr; p < endaddr;)
retval = (retval << 8) | * p ++;
unsigned char * startaddr = (unsigned char *)addr;
unsigned char * endaddr = startaddr + len;
+ if (! target_big_endian)
+ {
+ for (p = startaddr; p < endaddr;)
+ {
+ * p ++ = val & 0xff;
+ val >>= 8;
+ }
+ }
+ else
{
for (p = endaddr; p > startaddr;)
{
Keeping this data in target byte order simplifies the register
read/write functions. Keeping this data in native order improves
the performance of the simulator. Simulation speed is deemed more
- important. */
+ important. */
/* The ordering of the mcore_regset structure is matched in the
gdb/config/mcore/tm-mcore.h file in the REGISTER_NAMES macro. */
cpu.asregs.exception = SIGBUS;
}
+ else if (! target_big_endian)
+ {
+ unsigned char * p = cpu.mem + x;
+ p[3] = v >> 24;
+ p[2] = v >> 16;
+ p[1] = v >> 8;
+ p[0] = v;
+ }
else
{
unsigned char * p = cpu.mem + x;
cpu.asregs.exception = SIGBUS;
}
+ else if (! target_big_endian)
+ {
+ unsigned char * p = cpu.mem + x;
+ p[1] = v >> 8;
+ p[0] = v;
+ }
else
{
unsigned char * p = cpu.mem + x;
}
}
-/* Read functions */
+/* Read functions. */
static int INLINE
rbat (x)
word x;
cpu.asregs.exception = SIGBUS;
return 0;
}
+ else if (! target_big_endian)
+ {
+ unsigned char * p = cpu.mem + x;
+ return (p[3] << 24) | (p[2] << 16) | (p[1] << 8) | p[0];
+ }
else
{
unsigned char * p = cpu.mem + x;
cpu.asregs.exception = SIGBUS;
return 0;
}
+ else if (! target_big_endian)
+ {
+ unsigned char * p = cpu.mem + x;
+ return (p[1] << 8) | p[0];
+ }
else
{
unsigned char * p = cpu.mem + x;
{
}
-/* default to a 8 Mbyte (== 2^23) memory space */
+/* Default to a 8 Mbyte (== 2^23) memory space. */
static int sim_memory_size = 23;
#define MEM_SIZE_FLOOR 64
if (cpu.mem)
free (cpu.mem);
- /* watch out for the '0 count' problem. There's probably a better
- way.. e.g., why do we use 64 here? */
- if (cpu.asregs.msize < 64) /* ensure a boundary */
+ /* Watch out for the '0 count' problem. There's probably a better
+ way.. e.g., why do we use 64 here? */
+ if (cpu.asregs.msize < 64) /* Ensure a boundary. */
cpu.mem = (unsigned char *) calloc (64, (64 + cpu.asregs.msize) / 64);
else
cpu.mem = (unsigned char *) calloc (64, cpu.asregs.msize / 64);
break;
case 6:
- a[0] = (unsigned long) (cpu.gr[4]);
+ a[0] = (unsigned long) (cpu.gr[PARM1]);
/* Watch out for debugger's files. */
if (is_opened (a[0]))
{
if (pc & 02)
{
+ if (! target_big_endian)
+ inst = ibuf >> 16;
+ else
inst = ibuf & 0xFFFF;
needfetch = 1;
}
else
{
+ if (! target_big_endian)
+ inst = ibuf & 0xFFFF;
+ else
inst = ibuf >> 16;
}
unsigned long dst, src;
dst = cpu.gr[RD];
src = cpu.gr[RS];
- dst = dst >> src;
+ /* We must not rely solely upon the native shift operations, since they
+ may not match the M*Core's behaviour on boundary conditions. */
+ dst = src > 31 ? 0 : dst >> src;
cpu.gr[RD] = dst;
}
break;
break;
case 0x1A: /* asr */
- cpu.gr[RD] = (long)cpu.gr[RD] >> cpu.gr[RS];
+ /* We must not rely solely upon the native shift operations, since they
+ may not match the M*Core's behaviour on boundary conditions. */
+ if (cpu.gr[RS] > 30)
+ cpu.gr[RD] = ((long) cpu.gr[RD]) < 0 ? -1 : 0;
+ else
+ cpu.gr[RD] = (long) cpu.gr[RD] >> cpu.gr[RS];
break;
case 0x1B: /* lsl */
- cpu.gr[RD] = cpu.gr[RD] << cpu.gr[RS];
+ /* We must not rely solely upon the native shift operations, since they
+ may not match the M*Core's behaviour on boundary conditions. */
+ cpu.gr[RD] = cpu.gr[RS] > 31 ? 0 : cpu.gr[RD] << cpu.gr[RS];
break;
case 0x1C: /* addu */
if (prog_bfd == NULL)
return SIM_RC_FAIL;
+ target_big_endian = bfd_big_endian (prog_bfd);
if (abfd == NULL)
bfd_close (prog_bfd);