#include "sim-main.h"
#include "targ-vals.h"
-/* The semantic code invokes this for invalid (unrecognized) instructions. */
+/* The semantic code invokes this for invalid (unrecognized) instructions.
+ CIA is the address with the invalid insn.
+ VPC is the virtual pc of the following insn. */
-void
-sim_engine_invalid_insn (SIM_CPU *current_cpu, IADDR cia)
+SEM_PC
+sim_engine_invalid_insn (SIM_CPU *current_cpu, IADDR cia, SEM_PC vpc)
{
SIM_DESC sd = CPU_STATE (current_cpu);
else
#endif
sim_engine_halt (sd, current_cpu, NULL, cia, sim_stopped, SIM_SIGILL);
+ return vpc;
}
/* Process an address exception. */
{
a_m32r_h_cr_set (current_cpu, H_CR_BBPC,
a_m32r_h_cr_get (current_cpu, H_CR_BPC));
- a_m32r_h_bpsw_set (current_cpu, a_m32r_h_psw_get (current_cpu));
- /* sm not changed */
- a_m32r_h_psw_set (current_cpu, a_m32r_h_psw_get (current_cpu) & 0x80);
+ if (MACH_NUM (CPU_MACH (current_cpu)) == MACH_M32R)
+ {
+ m32rbf_h_bpsw_set (current_cpu, m32rbf_h_psw_get (current_cpu));
+ /* sm not changed */
+ m32rbf_h_psw_set (current_cpu, m32rbf_h_psw_get (current_cpu) & 0x80);
+ }
+ else
+ {
+ m32rxf_h_bpsw_set (current_cpu, m32rxf_h_psw_get (current_cpu));
+ /* sm not changed */
+ m32rxf_h_psw_set (current_cpu, m32rxf_h_psw_get (current_cpu) & 0x80);
+ }
a_m32r_h_cr_set (current_cpu, H_CR_BPC, cia);
sim_engine_restart (CPU_STATE (current_cpu), current_cpu, NULL,