#include "sim-main.h"
#include "targ-vals.h"
-/* The semantic code invokes this for illegal (unrecognized) instructions. */
+/* The semantic code invokes this for invalid (unrecognized) instructions.
+ CIA is the address with the invalid insn.
+ VPC is the virtual pc of the following insn. */
-void
-sim_engine_illegal_insn (SIM_CPU *current_cpu, PCADDR cia)
+SEM_PC
+sim_engine_invalid_insn (SIM_CPU *current_cpu, IADDR cia, SEM_PC vpc)
{
SIM_DESC sd = CPU_STATE (current_cpu);
else
#endif
sim_engine_halt (sd, current_cpu, NULL, cia, sim_stopped, SIM_SIGILL);
+ return vpc;
}
/* Process an address exception. */
unsigned int map, int nr_bytes, address_word addr,
transfer_type transfer, sim_core_signals sig)
{
-#if 0
if (STATE_ENVIRONMENT (sd) == OPERATING_ENVIRONMENT)
{
- h_bsm_set (current_cpu, h_sm_get (current_cpu));
- h_bie_set (current_cpu, h_ie_get (current_cpu));
- h_bcond_set (current_cpu, h_cond_get (current_cpu));
- /* sm not changed */
- h_ie_set (current_cpu, 0);
- h_cond_set (current_cpu, 0);
-
- h_bpc_set (current_cpu, cia);
+ a_m32r_h_cr_set (current_cpu, H_CR_BBPC,
+ a_m32r_h_cr_get (current_cpu, H_CR_BPC));
+ if (MACH_NUM (CPU_MACH (current_cpu)) == MACH_M32R)
+ {
+ m32rbf_h_bpsw_set (current_cpu, m32rbf_h_psw_get (current_cpu));
+ /* sm not changed */
+ m32rbf_h_psw_set (current_cpu, m32rbf_h_psw_get (current_cpu) & 0x80);
+ }
+ else
+ {
+ m32rxf_h_bpsw_set (current_cpu, m32rxf_h_psw_get (current_cpu));
+ /* sm not changed */
+ m32rxf_h_psw_set (current_cpu, m32rxf_h_psw_get (current_cpu) & 0x80);
+ }
+ a_m32r_h_cr_set (current_cpu, H_CR_BPC, cia);
sim_engine_restart (CPU_STATE (current_cpu), current_cpu, NULL,
EIT_ADDR_EXCP_ADDR);
}
else
-#endif
sim_core_signal (sd, current_cpu, cia, map, nr_bytes, addr,
transfer, sig);
}
Preprocessing like saving the various registers has already been done. */
USI
-a_m32r_trap (SIM_CPU *current_cpu, int num)
+m32r_trap (SIM_CPU *current_cpu, PCADDR pc, int num)
{
SIM_DESC sd = CPU_STATE (current_cpu);
host_callback *cb = STATE_CALLBACK (sd);
{
/* First try sim-break.c. If it's a breakpoint the simulator "owns"
it doesn't return. Otherwise it returns and let's us try. */
- sim_handle_breakpoint (sd, current_cpu, sim_pc_get (current_cpu));
+ sim_handle_breakpoint (sd, current_cpu, pc);
/* Fall through. */
}
#endif
CB_SYSCALL s;
CB_SYSCALL_INIT (&s);
- s.func = h_gr_get (current_cpu, 0);
- s.arg1 = h_gr_get (current_cpu, 1);
- s.arg2 = h_gr_get (current_cpu, 2);
- s.arg3 = h_gr_get (current_cpu, 3);
+ s.func = a_m32r_h_gr_get (current_cpu, 0);
+ s.arg1 = a_m32r_h_gr_get (current_cpu, 1);
+ s.arg2 = a_m32r_h_gr_get (current_cpu, 2);
+ s.arg3 = a_m32r_h_gr_get (current_cpu, 3);
if (s.func == TARGET_SYS_exit)
{
- sim_engine_halt (sd, current_cpu, NULL, sim_pc_get (current_cpu),
- sim_exited, s.arg1);
+ sim_engine_halt (sd, current_cpu, NULL, pc, sim_exited, s.arg1);
}
s.p1 = (PTR) sd;
s.p2 = (PTR) current_cpu;
s.read_mem = syscall_read_mem;
s.write_mem = syscall_write_mem;
- cb_syscall (STATE_CALLBACK (sd), &s);
- h_gr_set (current_cpu, 2, s.errcode);
- h_gr_set (current_cpu, 0, s.result);
- h_gr_set (current_cpu, 1, s.result2);
+ cb_syscall (cb, &s);
+ a_m32r_h_gr_set (current_cpu, 2, s.errcode);
+ a_m32r_h_gr_set (current_cpu, 0, s.result);
+ a_m32r_h_gr_set (current_cpu, 1, s.result2);
break;
}
case TRAP_BREAKPOINT:
- sim_engine_halt (sd, current_cpu, NULL, NULL_CIA,
+ sim_engine_halt (sd, current_cpu, NULL, pc,
sim_stopped, SIM_SIGTRAP);
break;
}
/* Fake an "rte" insn. */
- return (sim_pc_get (current_cpu) & -4) + 4;
+ /* FIXME: Should duplicate all of rte processing. */
+ return (pc & -4) + 4;
}