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[external/binutils.git] / sim / frv / cache.h

diff --git a/sim/frv/cache.h b/sim/frv/cache.h
index e45ae94..98d388d 100644 (file)
--- a/sim/frv/cache.h
+++ b/sim/frv/cache.h
@@ -1,22 +1,21 @@
 /* Cache support for the FRV simulator
-   Copyright (C) 1999, 2000 Free Software Foundation, Inc.
+   Copyright (C) 1999, 2000, 2003, 2007, 2008 Free Software Foundation, Inc.
    Contributed by Red Hat.
 
 This file is part of the GNU Simulators.
 
 This program is free software; you can redistribute it and/or modify
 it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
+the Free Software Foundation; either version 3 of the License, or
+(at your option) any later version.
 
 This program is distributed in the hope that it will be useful,
 but WITHOUT ANY WARRANTY; without even the implied warranty of
 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 GNU General Public License for more details.
 
-You should have received a copy of the GNU General Public License along
-with this program; if not, write to the Free Software Foundation, Inc.,
-59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+You should have received a copy of the GNU General Public License
+along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
 
 #ifndef CACHE_H
 #define CACHE_H
@@ -165,6 +164,8 @@ typedef struct {
 */
 typedef struct {
   SIM_CPU *cpu;
+  unsigned configured_ways;   /* Number of ways configured in each set.  */
+  unsigned configured_sets;   /* Number of sets configured in the cache.  */
   unsigned ways;              /* Number of ways in each set.  */
   unsigned sets;              /* Number of sets in the cache.  */
   unsigned line_size;         /* Size of each cache line.  */
@@ -200,14 +201,15 @@ typedef struct {
 
 #define CACHE_RETURN_DATA(cache, slot, address, mode, N) (               \
   T2H_##N (*(mode *)(& (cache)->pipeline[slot].status.return_buffer.data \
-                    [((address) & ((cache)->line_size - 1)              \
-                      & ~(sizeof (mode) - 1))]))                        \
+                    [((address) & ((cache)->line_size - 1))]))          \
 )
-
 #define CACHE_RETURN_DATA_ADDRESS(cache, slot, address, N) (              \
   ((void *)& (cache)->pipeline[slot].status.return_buffer.data[(address)  \
-                                              & ((cache)->line_size - 1) \
-                                              & ~((N) - 1)])             \
+                                              & ((cache)->line_size - 1)]) \
+)
+
+#define DATA_CROSSES_CACHE_LINE(cache, address, size) ( \
+  ((address) & ((cache)->line_size - 1)) + (size) > (cache)->line_size \
 )
 
 #define CACHE_INITIALIZED(cache) ((cache)->data_storage != NULL)
@@ -217,6 +219,8 @@ void
 frv_cache_init (SIM_CPU *, FRV_CACHE *);
 void
 frv_cache_term (FRV_CACHE *);
+void
+frv_cache_reconfigure (SIM_CPU *, FRV_CACHE *);
 int
 frv_cache_enabled (FRV_CACHE *);