Add support to GDB for the Renesas rl78 architecture.

[external/binutils.git] / sim / cris / semcrisv10f-switch.c

diff --git a/sim/cris/semcrisv10f-switch.c b/sim/cris/semcrisv10f-switch.c
index 968e10b..dd904ee 100644 (file)
--- a/sim/cris/semcrisv10f-switch.c
+++ b/sim/cris/semcrisv10f-switch.c
@@ -2,22 +2,23 @@
 
 THIS FILE IS MACHINE GENERATED WITH CGEN.
 
-Copyright 1996-2005 Free Software Foundation, Inc.
+Copyright 1996-2010, 2012 Free Software Foundation, Inc.
 
 This file is part of the GNU simulators.
 
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 3 of the License, or
-(at your option) any later version.
+   This file is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3, or (at your option)
+   any later version.
 
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
+   It is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
 
-You should have received a copy of the GNU General Public License
-along with this program.  If not, see <http://www.gnu.org/licenses/>.
+   You should have received a copy of the GNU General Public License along
+   with this program; if not, write to the Free Software Foundation, Inc.,
+   51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
 
 */
 
@@ -270,11 +271,7 @@ along with this program.  If not, see <http://www.gnu.org/licenses/>.
 #endif
 
 #undef GET_ATTR
-#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
 #define GET_ATTR(cpu, num, attr) CGEN_ATTR_VALUE (NULL, abuf->idesc->attrs, CGEN_INSN_##attr)
-#else
-#define GET_ATTR(cpu, num, attr) CGEN_ATTR_VALUE (NULL, abuf->idesc->attrs, CGEN_INSN_/**/attr)
-#endif
 
 {
 
@@ -305,7 +302,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case)
 {
   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_empty.f
+#define FLD(f) abuf->fields.sfmt_empty.f
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
   vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
@@ -330,7 +327,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case)
 {
   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_empty.f
+#define FLD(f) abuf->fields.sfmt_empty.f
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
   vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
@@ -349,7 +346,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case)
 {
   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_empty.f
+#define FLD(f) abuf->fields.sfmt_empty.f
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
   vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
@@ -368,7 +365,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case)
 {
   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_empty.f
+#define FLD(f) abuf->fields.sfmt_empty.f
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
   vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
@@ -396,7 +393,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case)
 {
   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_empty.f
+#define FLD(f) abuf->fields.sfmt_empty.f
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
   vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
@@ -418,7 +415,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case)
 {
   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_empty.f
+#define FLD(f) abuf->fields.sfmt_empty.f
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
   vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
@@ -447,7 +444,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case)
 {
   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_empty.f
+#define FLD(f) abuf->fields.sfmt_empty.f
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
@@ -726,10 +723,12 @@ SET_H_VBIT_MOVE (0);
   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 
 {
-  QI tmp_newval;
-  tmp_newval = GET_H_GR (FLD (f_operand1));
+  QI tmp_tmpops;
+  SI tmp_newval;
+  tmp_tmpops = GET_H_GR (FLD (f_operand1));
+  tmp_newval = EXTQISI (tmp_tmpops);
   {
-    SI opval = EXTQISI (tmp_newval);
+    SI opval = tmp_newval;
     SET_H_GR (FLD (f_operand2), opval);
     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
   }
@@ -775,10 +774,12 @@ SET_H_VBIT_MOVE (0);
   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 
 {
-  HI tmp_newval;
-  tmp_newval = GET_H_GR (FLD (f_operand1));
+  HI tmp_tmpops;
+  SI tmp_newval;
+  tmp_tmpops = GET_H_GR (FLD (f_operand1));
+  tmp_newval = EXTHISI (tmp_tmpops);
   {
-    SI opval = EXTHISI (tmp_newval);
+    SI opval = tmp_newval;
     SET_H_GR (FLD (f_operand2), opval);
     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
   }
@@ -824,10 +825,12 @@ SET_H_VBIT_MOVE (0);
   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 
 {
-  QI tmp_newval;
-  tmp_newval = GET_H_GR (FLD (f_operand1));
+  QI tmp_tmpops;
+  SI tmp_newval;
+  tmp_tmpops = GET_H_GR (FLD (f_operand1));
+  tmp_newval = ZEXTQISI (tmp_tmpops);
   {
-    SI opval = ZEXTQISI (tmp_newval);
+    SI opval = tmp_newval;
     SET_H_GR (FLD (f_operand2), opval);
     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
   }
@@ -873,10 +876,12 @@ SET_H_VBIT_MOVE (0);
   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 
 {
-  HI tmp_newval;
-  tmp_newval = GET_H_GR (FLD (f_operand1));
+  HI tmp_tmpops;
+  SI tmp_newval;
+  tmp_tmpops = GET_H_GR (FLD (f_operand1));
+  tmp_newval = ZEXTHISI (tmp_tmpops);
   {
-    SI opval = ZEXTHISI (tmp_newval);
+    SI opval = tmp_newval;
     SET_H_GR (FLD (f_operand2), opval);
     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
   }
@@ -4624,7 +4629,7 @@ cgen_rtx_error (current_cpu, "write from unimplemented special register");
 {
   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_empty.f
+#define FLD(f) abuf->fields.sfmt_empty.f
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
@@ -6469,7 +6474,7 @@ if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
 {
   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_empty.f
+#define FLD(f) abuf->fields.sfmt_empty.f
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
   SEM_BRANCH_INIT