THIS FILE IS MACHINE GENERATED WITH CGEN.
-Copyright 1996-2005 Free Software Foundation, Inc.
+Copyright 1996-2010, 2012 Free Software Foundation, Inc.
This file is part of the GNU simulators.
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
+ This file is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3, or (at your option)
+ any later version.
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
+ It is distributed in the hope that it will be useful, but WITHOUT
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ License for more details.
-You should have received a copy of the GNU General Public License along
-with this program; if not, write to the Free Software Foundation, Inc.,
-51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
+ You should have received a copy of the GNU General Public License along
+ with this program; if not, write to the Free Software Foundation, Inc.,
+ 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
*/
{ CRISV10F_INSN_MOVE_SPR_RV10, && case_sem_INSN_MOVE_SPR_RV10 },
{ CRISV10F_INSN_RET_TYPE, && case_sem_INSN_RET_TYPE },
{ CRISV10F_INSN_MOVE_M_SPRV10, && case_sem_INSN_MOVE_M_SPRV10 },
- { CRISV10F_INSN_MOVE_C_SPRV10_P0, && case_sem_INSN_MOVE_C_SPRV10_P0 },
- { CRISV10F_INSN_MOVE_C_SPRV10_P1, && case_sem_INSN_MOVE_C_SPRV10_P1 },
- { CRISV10F_INSN_MOVE_C_SPRV10_P4, && case_sem_INSN_MOVE_C_SPRV10_P4 },
{ CRISV10F_INSN_MOVE_C_SPRV10_P5, && case_sem_INSN_MOVE_C_SPRV10_P5 },
- { CRISV10F_INSN_MOVE_C_SPRV10_P8, && case_sem_INSN_MOVE_C_SPRV10_P8 },
{ CRISV10F_INSN_MOVE_C_SPRV10_P9, && case_sem_INSN_MOVE_C_SPRV10_P9 },
{ CRISV10F_INSN_MOVE_C_SPRV10_P10, && case_sem_INSN_MOVE_C_SPRV10_P10 },
{ CRISV10F_INSN_MOVE_C_SPRV10_P11, && case_sem_INSN_MOVE_C_SPRV10_P11 },
{ CRISV10F_INSN_LZ, && case_sem_INSN_LZ },
{ CRISV10F_INSN_ADDOQ, && case_sem_INSN_ADDOQ },
{ CRISV10F_INSN_BDAPQPC, && case_sem_INSN_BDAPQPC },
+ { CRISV10F_INSN_BDAP_32_PC, && case_sem_INSN_BDAP_32_PC },
+ { CRISV10F_INSN_MOVE_M_PCPLUS_P0, && case_sem_INSN_MOVE_M_PCPLUS_P0 },
+ { CRISV10F_INSN_MOVE_M_SPPLUS_P8, && case_sem_INSN_MOVE_M_SPPLUS_P8 },
{ CRISV10F_INSN_ADDO_M_B_M, && case_sem_INSN_ADDO_M_B_M },
{ CRISV10F_INSN_ADDO_M_W_M, && case_sem_INSN_ADDO_M_W_M },
{ CRISV10F_INSN_ADDO_M_D_M, && case_sem_INSN_ADDO_M_D_M },
#endif
#undef GET_ATTR
-#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
#define GET_ATTR(cpu, num, attr) CGEN_ATTR_VALUE (NULL, abuf->idesc->attrs, CGEN_INSN_##attr)
-#else
-#define GET_ATTR(cpu, num, attr) CGEN_ATTR_VALUE (NULL, abuf->idesc->attrs, CGEN_INSN_/**/attr)
-#endif
{
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_empty.f
+#define FLD(f) abuf->fields.sfmt_empty.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_empty.f
+#define FLD(f) abuf->fields.sfmt_empty.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_empty.f
+#define FLD(f) abuf->fields.sfmt_empty.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_empty.f
+#define FLD(f) abuf->fields.sfmt_empty.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_empty.f
+#define FLD(f) abuf->fields.sfmt_empty.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_empty.f
+#define FLD(f) abuf->fields.sfmt_empty.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_empty.f
+#define FLD(f) abuf->fields.sfmt_empty.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
{
- QI tmp_newval;
- tmp_newval = GET_H_GR (FLD (f_operand1));
+ QI tmp_tmpops;
+ SI tmp_newval;
+ tmp_tmpops = GET_H_GR (FLD (f_operand1));
+ tmp_newval = EXTQISI (tmp_tmpops);
{
- SI opval = EXTQISI (tmp_newval);
+ SI opval = tmp_newval;
SET_H_GR (FLD (f_operand2), opval);
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
}
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
{
- HI tmp_newval;
- tmp_newval = GET_H_GR (FLD (f_operand1));
+ HI tmp_tmpops;
+ SI tmp_newval;
+ tmp_tmpops = GET_H_GR (FLD (f_operand1));
+ tmp_newval = EXTHISI (tmp_tmpops);
{
- SI opval = EXTHISI (tmp_newval);
+ SI opval = tmp_newval;
SET_H_GR (FLD (f_operand2), opval);
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
}
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
{
- QI tmp_newval;
- tmp_newval = GET_H_GR (FLD (f_operand1));
+ QI tmp_tmpops;
+ SI tmp_newval;
+ tmp_tmpops = GET_H_GR (FLD (f_operand1));
+ tmp_newval = ZEXTQISI (tmp_tmpops);
{
- SI opval = ZEXTQISI (tmp_newval);
+ SI opval = tmp_newval;
SET_H_GR (FLD (f_operand2), opval);
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
}
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
{
- HI tmp_newval;
- tmp_newval = GET_H_GR (FLD (f_operand1));
+ HI tmp_tmpops;
+ SI tmp_newval;
+ tmp_tmpops = GET_H_GR (FLD (f_operand1));
+ tmp_newval = ZEXTHISI (tmp_tmpops);
{
- SI opval = ZEXTHISI (tmp_newval);
+ SI opval = tmp_newval;
SET_H_GR (FLD (f_operand2), opval);
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
}
SI tmp_newval;
tmp_prno = FLD (f_operand2);
tmp_newval = GET_H_SR (FLD (f_operand2));
-if (EQSI (tmp_prno, 0)) {
+if (EQSI (tmp_prno, 5)) {
{
SI tmp_oldregval;
tmp_oldregval = GET_H_RAW_GR_PC (FLD (f_operand1));
{
- SI opval = ORSI (ANDSI (tmp_newval, 255), ANDSI (tmp_oldregval, 0xffffff00));
+ SI opval = ORSI (ANDSI (tmp_newval, 65535), ANDSI (tmp_oldregval, 0xffff0000));
SET_H_GR (FLD (f_operand1), opval);
written |= (1 << 4);
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
}
}
}
- else if (EQSI (tmp_prno, 1)) {
-{
- SI tmp_oldregval;
- tmp_oldregval = GET_H_RAW_GR_PC (FLD (f_operand1));
+ else if (EQSI (tmp_prno, 9)) {
{
- SI opval = ORSI (ANDSI (tmp_newval, 255), ANDSI (tmp_oldregval, 0xffffff00));
+ SI opval = tmp_newval;
SET_H_GR (FLD (f_operand1), opval);
written |= (1 << 4);
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
}
}
-}
- else if (EQSI (tmp_prno, 4)) {
-{
- SI tmp_oldregval;
- tmp_oldregval = GET_H_RAW_GR_PC (FLD (f_operand1));
+ else if (EQSI (tmp_prno, 10)) {
{
- SI opval = ORSI (ANDSI (tmp_newval, 65535), ANDSI (tmp_oldregval, 0xffff0000));
+ SI opval = tmp_newval;
SET_H_GR (FLD (f_operand1), opval);
written |= (1 << 4);
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
}
}
-}
- else if (EQSI (tmp_prno, 5)) {
-{
- SI tmp_oldregval;
- tmp_oldregval = GET_H_RAW_GR_PC (FLD (f_operand1));
+ else if (EQSI (tmp_prno, 11)) {
{
- SI opval = ORSI (ANDSI (tmp_newval, 65535), ANDSI (tmp_oldregval, 0xffff0000));
+ SI opval = tmp_newval;
SET_H_GR (FLD (f_operand1), opval);
written |= (1 << 4);
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
}
}
-}
- else if (EQSI (tmp_prno, 8)) {
+ else if (EQSI (tmp_prno, 12)) {
{
SI opval = tmp_newval;
SET_H_GR (FLD (f_operand1), opval);
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
}
}
- else if (EQSI (tmp_prno, 9)) {
+ else if (EQSI (tmp_prno, 13)) {
{
SI opval = tmp_newval;
SET_H_GR (FLD (f_operand1), opval);
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
}
}
- else if (EQSI (tmp_prno, 10)) {
+ else if (EQSI (tmp_prno, 0)) {
+{
+ SI tmp_oldregval;
+ tmp_oldregval = GET_H_RAW_GR_PC (FLD (f_operand1));
{
- SI opval = tmp_newval;
+ SI opval = ORSI (ANDSI (tmp_newval, 255), ANDSI (tmp_oldregval, 0xffffff00));
SET_H_GR (FLD (f_operand1), opval);
written |= (1 << 4);
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
}
}
- else if (EQSI (tmp_prno, 11)) {
+}
+ else if (EQSI (tmp_prno, 1)) {
+{
+ SI tmp_oldregval;
+ tmp_oldregval = GET_H_RAW_GR_PC (FLD (f_operand1));
{
- SI opval = tmp_newval;
+ SI opval = ORSI (ANDSI (tmp_newval, 255), ANDSI (tmp_oldregval, 0xffffff00));
SET_H_GR (FLD (f_operand1), opval);
written |= (1 << 4);
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
}
}
- else if (EQSI (tmp_prno, 12)) {
+}
+ else if (EQSI (tmp_prno, 4)) {
+{
+ SI tmp_oldregval;
+ tmp_oldregval = GET_H_RAW_GR_PC (FLD (f_operand1));
{
- SI opval = tmp_newval;
+ SI opval = ORSI (ANDSI (tmp_newval, 65535), ANDSI (tmp_oldregval, 0xffff0000));
SET_H_GR (FLD (f_operand1), opval);
written |= (1 << 4);
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
}
}
- else if (EQSI (tmp_prno, 13)) {
+}
+ else if (EQSI (tmp_prno, 8)) {
{
SI opval = tmp_newval;
SET_H_GR (FLD (f_operand1), opval);
SI tmp_rno;
SI tmp_newval;
tmp_rno = FLD (f_operand2);
-if (EQSI (tmp_rno, 0)) {
- tmp_newval = EXTQISI (({ SI tmp_addr;
- QI tmp_tmp_mem;
- BI tmp_postinc;
- tmp_postinc = FLD (f_memmode);
-; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
-; tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
-; if (NEBI (tmp_postinc, 0)) {
-{
-if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
- tmp_addr = ADDSI (tmp_addr, 1);
-}
- {
- SI opval = tmp_addr;
- SET_H_GR (FLD (f_operand1), opval);
- written |= (1 << 9);
- TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
- }
-}
-}
-; tmp_tmp_mem; }));
-}
- else if (EQSI (tmp_rno, 1)) {
- tmp_newval = EXTQISI (({ SI tmp_addr;
- QI tmp_tmp_mem;
- BI tmp_postinc;
- tmp_postinc = FLD (f_memmode);
-; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
-; tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
-; if (NEBI (tmp_postinc, 0)) {
-{
-if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
- tmp_addr = ADDSI (tmp_addr, 1);
-}
- {
- SI opval = tmp_addr;
- SET_H_GR (FLD (f_operand1), opval);
- written |= (1 << 9);
- TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
- }
-}
-}
-; tmp_tmp_mem; }));
-}
- else if (EQSI (tmp_rno, 4)) {
+if (EQSI (tmp_rno, 5)) {
tmp_newval = EXTHISI (({ SI tmp_addr;
HI tmp_tmp_mem;
BI tmp_postinc;
{
SI opval = tmp_addr;
SET_H_GR (FLD (f_operand1), opval);
- written |= (1 << 9);
- TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
- }
-}
-}
-; tmp_tmp_mem; }));
-}
- else if (EQSI (tmp_rno, 5)) {
- tmp_newval = EXTHISI (({ SI tmp_addr;
- HI tmp_tmp_mem;
- BI tmp_postinc;
- tmp_postinc = FLD (f_memmode);
-; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
-; tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr);
-; if (NEBI (tmp_postinc, 0)) {
-{
-if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
- tmp_addr = ADDSI (tmp_addr, 2);
-}
- {
- SI opval = tmp_addr;
- SET_H_GR (FLD (f_operand1), opval);
- written |= (1 << 9);
+ written |= (1 << 8);
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
}
}
}
; tmp_tmp_mem; }));
}
- else if (EQSI (tmp_rno, 8)) {
- tmp_newval = ({ SI tmp_addr;
- SI tmp_tmp_mem;
- BI tmp_postinc;
- tmp_postinc = FLD (f_memmode);
-; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
-; tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
-; if (NEBI (tmp_postinc, 0)) {
-{
-if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
- tmp_addr = ADDSI (tmp_addr, 4);
-}
- {
- SI opval = tmp_addr;
- SET_H_GR (FLD (f_operand1), opval);
- written |= (1 << 9);
- TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
- }
-}
-}
-; tmp_tmp_mem; });
-}
else if (EQSI (tmp_rno, 9)) {
tmp_newval = ({ SI tmp_addr;
SI tmp_tmp_mem;
{
SI opval = tmp_addr;
SET_H_GR (FLD (f_operand1), opval);
- written |= (1 << 9);
+ written |= (1 << 8);
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
}
}
{
SI opval = tmp_addr;
SET_H_GR (FLD (f_operand1), opval);
- written |= (1 << 9);
+ written |= (1 << 8);
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
}
}
{
SI opval = tmp_addr;
SET_H_GR (FLD (f_operand1), opval);
- written |= (1 << 9);
+ written |= (1 << 8);
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
}
}
{
SI opval = tmp_addr;
SET_H_GR (FLD (f_operand1), opval);
- written |= (1 << 9);
+ written |= (1 << 8);
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
}
}
{
SI opval = tmp_addr;
SET_H_GR (FLD (f_operand1), opval);
- written |= (1 << 9);
+ written |= (1 << 8);
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
}
}
{
SI opval = tmp_addr;
SET_H_GR (FLD (f_operand1), opval);
- written |= (1 << 9);
+ written |= (1 << 8);
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
}
}
{
SI opval = tmp_addr;
SET_H_GR (FLD (f_operand1), opval);
- written |= (1 << 9);
+ written |= (1 << 8);
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
}
}
{
SI opval = tmp_addr;
SET_H_GR (FLD (f_operand1), opval);
- written |= (1 << 9);
+ written |= (1 << 8);
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
}
}
}
-; tmp_tmp_mem; });
-}
- else {
-cgen_rtx_error (current_cpu, "Trying to set unimplemented special register");
-}
- {
- SI opval = tmp_newval;
- SET_H_SR (FLD (f_operand2), opval);
- TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
- }
-{
- {
- BI opval = 0;
- CPU (h_xbit) = opval;
- TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
- }
- {
- BI opval = 0;
- SET_H_INSN_PREFIXED_P (opval);
- TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
- }
-}
-}
-
- abuf->written = written;
-#undef FLD
-}
- NEXT (vpc);
-
- CASE (sem, INSN_MOVE_C_SPRV10_P0) : /* move ${sconst8},${Pd} */
-{
- SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
- ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_move_c_sprv10_p0.f
- int UNUSED written = 0;
- IADDR UNUSED pc = abuf->addr;
- vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-{
- {
- SI opval = FLD (f_indir_pc__byte);
- SET_H_SR (FLD (f_operand2), opval);
- TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
- }
-{
- {
- BI opval = 0;
- CPU (h_xbit) = opval;
- TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
- }
- {
- BI opval = 0;
- SET_H_INSN_PREFIXED_P (opval);
- TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
- }
-}
-}
-
-#undef FLD
-}
- NEXT (vpc);
-
- CASE (sem, INSN_MOVE_C_SPRV10_P1) : /* move ${sconst8},${Pd} */
-{
- SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
- ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_move_c_sprv10_p0.f
- int UNUSED written = 0;
- IADDR UNUSED pc = abuf->addr;
- vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-{
- {
- SI opval = FLD (f_indir_pc__byte);
- SET_H_SR (FLD (f_operand2), opval);
- TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
- }
-{
- {
- BI opval = 0;
- CPU (h_xbit) = opval;
- TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
- }
- {
- BI opval = 0;
- SET_H_INSN_PREFIXED_P (opval);
- TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
- }
-}
-}
-
-#undef FLD
-}
- NEXT (vpc);
-
- CASE (sem, INSN_MOVE_C_SPRV10_P4) : /* move ${sconst16},${Pd} */
-{
- SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
- ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_move_c_sprv10_p4.f
- int UNUSED written = 0;
- IADDR UNUSED pc = abuf->addr;
- vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-{
- {
- SI opval = FLD (f_indir_pc__word);
- SET_H_SR (FLD (f_operand2), opval);
- TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
- }
-{
- {
- BI opval = 0;
- CPU (h_xbit) = opval;
- TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
- }
- {
- BI opval = 0;
- SET_H_INSN_PREFIXED_P (opval);
- TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
- }
-}
-}
-
-#undef FLD
-}
- NEXT (vpc);
-
- CASE (sem, INSN_MOVE_C_SPRV10_P5) : /* move ${sconst16},${Pd} */
-{
- SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
- ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_move_c_sprv10_p4.f
- int UNUSED written = 0;
- IADDR UNUSED pc = abuf->addr;
- vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-{
+; tmp_tmp_mem; });
+}
+ else {
+cgen_rtx_error (current_cpu, "Trying to set unimplemented special register");
+}
{
- SI opval = FLD (f_indir_pc__word);
+ SI opval = tmp_newval;
SET_H_SR (FLD (f_operand2), opval);
TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
}
}
}
+ abuf->written = written;
#undef FLD
}
NEXT (vpc);
- CASE (sem, INSN_MOVE_C_SPRV10_P8) : /* move ${const32},${Pd} */
+ CASE (sem, INSN_MOVE_C_SPRV10_P5) : /* move ${sconst16},${Pd} */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_move_c_sprv10_p8.f
+#define FLD(f) abuf->fields.sfmt_move_c_sprv10_p5.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
- vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
{
- SI opval = FLD (f_indir_pc__dword);
+ SI opval = FLD (f_indir_pc__word);
SET_H_SR (FLD (f_operand2), opval);
TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
}
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_move_c_sprv10_p8.f
+#define FLD(f) abuf->fields.sfmt_move_c_sprv10_p9.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_move_c_sprv10_p8.f
+#define FLD(f) abuf->fields.sfmt_move_c_sprv10_p9.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_move_c_sprv10_p8.f
+#define FLD(f) abuf->fields.sfmt_move_c_sprv10_p9.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_move_c_sprv10_p8.f
+#define FLD(f) abuf->fields.sfmt_move_c_sprv10_p9.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_move_c_sprv10_p8.f
+#define FLD(f) abuf->fields.sfmt_move_c_sprv10_p9.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_move_c_sprv10_p8.f
+#define FLD(f) abuf->fields.sfmt_move_c_sprv10_p9.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_move_c_sprv10_p8.f
+#define FLD(f) abuf->fields.sfmt_move_c_sprv10_p9.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_move_c_sprv10_p8.f
+#define FLD(f) abuf->fields.sfmt_move_c_sprv10_p9.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
{
SI tmp_rno;
tmp_rno = FLD (f_operand2);
-if (EQSI (tmp_rno, 0)) {
+if (EQSI (tmp_rno, 5)) {
{
SI tmp_addr;
BI tmp_postinc;
if (EQBI (CPU (h_pbit), 0)) {
{
{
- QI opval = GET_H_SR (FLD (f_operand2));
- SETMEMQI (current_cpu, pc, tmp_addr, opval);
- written |= (1 << 12);
+ HI opval = GET_H_SR (FLD (f_operand2));
+ SETMEMHI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 11);
TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
}
{
}
} else {
{
- QI opval = GET_H_SR (FLD (f_operand2));
- SETMEMQI (current_cpu, pc, tmp_addr, opval);
- written |= (1 << 12);
+ HI opval = GET_H_SR (FLD (f_operand2));
+ SETMEMHI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 11);
TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
}
}
if (NEBI (tmp_postinc, 0)) {
{
if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
- tmp_addr = ADDSI (tmp_addr, 1);
+ tmp_addr = ADDSI (tmp_addr, 2);
}
{
SI opval = tmp_addr;
}
}
}
- else if (EQSI (tmp_rno, 1)) {
+ else if (EQSI (tmp_rno, 9)) {
{
SI tmp_addr;
BI tmp_postinc;
if (EQBI (CPU (h_pbit), 0)) {
{
{
- QI opval = GET_H_SR (FLD (f_operand2));
- SETMEMQI (current_cpu, pc, tmp_addr, opval);
- written |= (1 << 12);
+ SI opval = GET_H_SR (FLD (f_operand2));
+ SETMEMSI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 13);
TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
}
{
}
} else {
{
- QI opval = GET_H_SR (FLD (f_operand2));
- SETMEMQI (current_cpu, pc, tmp_addr, opval);
- written |= (1 << 12);
+ SI opval = GET_H_SR (FLD (f_operand2));
+ SETMEMSI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 13);
TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
}
}
if (NEBI (tmp_postinc, 0)) {
{
if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
- tmp_addr = ADDSI (tmp_addr, 1);
+ tmp_addr = ADDSI (tmp_addr, 4);
}
{
SI opval = tmp_addr;
}
}
}
- else if (EQSI (tmp_rno, 4)) {
+ else if (EQSI (tmp_rno, 10)) {
{
SI tmp_addr;
BI tmp_postinc;
if (EQBI (CPU (h_pbit), 0)) {
{
{
- HI opval = GET_H_SR (FLD (f_operand2));
- SETMEMHI (current_cpu, pc, tmp_addr, opval);
- written |= (1 << 11);
+ SI opval = GET_H_SR (FLD (f_operand2));
+ SETMEMSI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 13);
TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
}
{
}
} else {
{
- HI opval = GET_H_SR (FLD (f_operand2));
- SETMEMHI (current_cpu, pc, tmp_addr, opval);
- written |= (1 << 11);
+ SI opval = GET_H_SR (FLD (f_operand2));
+ SETMEMSI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 13);
TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
}
}
if (NEBI (tmp_postinc, 0)) {
{
if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
- tmp_addr = ADDSI (tmp_addr, 2);
+ tmp_addr = ADDSI (tmp_addr, 4);
}
{
SI opval = tmp_addr;
}
}
}
- else if (EQSI (tmp_rno, 5)) {
+ else if (EQSI (tmp_rno, 11)) {
{
SI tmp_addr;
BI tmp_postinc;
if (EQBI (CPU (h_pbit), 0)) {
{
{
- HI opval = GET_H_SR (FLD (f_operand2));
- SETMEMHI (current_cpu, pc, tmp_addr, opval);
- written |= (1 << 11);
+ SI opval = GET_H_SR (FLD (f_operand2));
+ SETMEMSI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 13);
TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
}
{
}
} else {
{
- HI opval = GET_H_SR (FLD (f_operand2));
- SETMEMHI (current_cpu, pc, tmp_addr, opval);
- written |= (1 << 11);
+ SI opval = GET_H_SR (FLD (f_operand2));
+ SETMEMSI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 13);
TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
}
}
if (NEBI (tmp_postinc, 0)) {
{
if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
- tmp_addr = ADDSI (tmp_addr, 2);
+ tmp_addr = ADDSI (tmp_addr, 4);
}
{
SI opval = tmp_addr;
}
}
}
- else if (EQSI (tmp_rno, 8)) {
+ else if (EQSI (tmp_rno, 12)) {
{
SI tmp_addr;
BI tmp_postinc;
}
}
}
- else if (EQSI (tmp_rno, 9)) {
+ else if (EQSI (tmp_rno, 13)) {
{
SI tmp_addr;
BI tmp_postinc;
}
}
}
- else if (EQSI (tmp_rno, 10)) {
+ else if (EQSI (tmp_rno, 0)) {
{
SI tmp_addr;
BI tmp_postinc;
if (EQBI (CPU (h_pbit), 0)) {
{
{
- SI opval = GET_H_SR (FLD (f_operand2));
- SETMEMSI (current_cpu, pc, tmp_addr, opval);
- written |= (1 << 13);
+ QI opval = GET_H_SR (FLD (f_operand2));
+ SETMEMQI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 12);
TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
}
{
}
} else {
{
- SI opval = GET_H_SR (FLD (f_operand2));
- SETMEMSI (current_cpu, pc, tmp_addr, opval);
- written |= (1 << 13);
+ QI opval = GET_H_SR (FLD (f_operand2));
+ SETMEMQI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 12);
TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
}
}
if (NEBI (tmp_postinc, 0)) {
{
if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
- tmp_addr = ADDSI (tmp_addr, 4);
+ tmp_addr = ADDSI (tmp_addr, 1);
}
{
SI opval = tmp_addr;
}
}
}
- else if (EQSI (tmp_rno, 11)) {
+ else if (EQSI (tmp_rno, 1)) {
{
SI tmp_addr;
BI tmp_postinc;
if (EQBI (CPU (h_pbit), 0)) {
{
{
- SI opval = GET_H_SR (FLD (f_operand2));
- SETMEMSI (current_cpu, pc, tmp_addr, opval);
- written |= (1 << 13);
+ QI opval = GET_H_SR (FLD (f_operand2));
+ SETMEMQI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 12);
TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
}
{
}
} else {
{
- SI opval = GET_H_SR (FLD (f_operand2));
- SETMEMSI (current_cpu, pc, tmp_addr, opval);
- written |= (1 << 13);
+ QI opval = GET_H_SR (FLD (f_operand2));
+ SETMEMQI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 12);
TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
}
}
if (NEBI (tmp_postinc, 0)) {
{
if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
- tmp_addr = ADDSI (tmp_addr, 4);
+ tmp_addr = ADDSI (tmp_addr, 1);
}
{
SI opval = tmp_addr;
}
}
}
- else if (EQSI (tmp_rno, 12)) {
+ else if (EQSI (tmp_rno, 4)) {
{
SI tmp_addr;
BI tmp_postinc;
if (EQBI (CPU (h_pbit), 0)) {
{
{
- SI opval = GET_H_SR (FLD (f_operand2));
- SETMEMSI (current_cpu, pc, tmp_addr, opval);
- written |= (1 << 13);
+ HI opval = GET_H_SR (FLD (f_operand2));
+ SETMEMHI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 11);
TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
}
{
}
} else {
{
- SI opval = GET_H_SR (FLD (f_operand2));
- SETMEMSI (current_cpu, pc, tmp_addr, opval);
- written |= (1 << 13);
+ HI opval = GET_H_SR (FLD (f_operand2));
+ SETMEMHI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 11);
TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
}
}
if (NEBI (tmp_postinc, 0)) {
{
if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
- tmp_addr = ADDSI (tmp_addr, 4);
+ tmp_addr = ADDSI (tmp_addr, 2);
}
{
SI opval = tmp_addr;
}
}
}
- else if (EQSI (tmp_rno, 13)) {
+ else if (EQSI (tmp_rno, 8)) {
{
SI tmp_addr;
BI tmp_postinc;
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_empty.f
+#define FLD(f) abuf->fields.sfmt_empty.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_move_c_sprv10_p8.f
+#define FLD(f) abuf->fields.sfmt_move_c_sprv10_p9.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
SEM_BRANCH_INIT
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_empty.f
+#define FLD(f) abuf->fields.sfmt_empty.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
SEM_BRANCH_INIT
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_move_c_sprv10_p8.f
+#define FLD(f) abuf->fields.sfmt_move_c_sprv10_p9.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
SEM_BRANCH_INIT
}
NEXT (vpc);
+ CASE (sem, INSN_BDAP_32_PC) : /* bdap ${sconst32},PC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_move_c_sprv10_p9.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
+
+{
+ SI tmp_newpc;
+ SI tmp_oldpc;
+ SI tmp_offs;
+ tmp_offs = FLD (f_indir_pc__dword);
+ tmp_oldpc = ADDSI (pc, 6);
+ tmp_newpc = ADDSI (tmp_oldpc, tmp_offs);
+ {
+ SI opval = tmp_newpc;
+ CPU (h_prefixreg_pre_v32) = opval;
+ TRACE_RESULT (current_cpu, abuf, "prefixreg", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOVE_M_PCPLUS_P0) : /* move [PC+],P0 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_move_m_spplus_p8.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+if (GET_H_INSN_PREFIXED_P ()) {
+{
+ QI tmp_dummy;
+ tmp_dummy = ({ SI tmp_addr;
+ QI tmp_tmp_mem;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (pc) : (CPU (h_prefixreg_pre_v32)));
+; tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
+; if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 1);
+}
+ {
+ USI opval = tmp_addr;
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 5);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+; tmp_tmp_mem; });
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ written |= (1 << 6);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+} else {
+cgen_rtx_error (current_cpu, "move [PC+],P0 without prefix is not implemented");
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOVE_M_SPPLUS_P8) : /* move [SP+],P8 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_move_m_spplus_p8.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+if (GET_H_INSN_PREFIXED_P ()) {
+{
+ SI tmp_dummy;
+ tmp_dummy = ({ SI tmp_addr;
+ SI tmp_tmp_mem;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (((UINT) 14))) : (CPU (h_prefixreg_pre_v32)));
+; tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
+; if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (((UINT) 14), opval);
+ written |= (1 << 5);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+; tmp_tmp_mem; });
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ written |= (1 << 6);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+} else {
+cgen_rtx_error (current_cpu, "move [SP+],P8 without prefix is not implemented");
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
CASE (sem, INSN_ADDO_M_B_M) : /* addo-m.b [${Rs}${inc}],$Rd,ACR */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_move_c_sprv10_p8.f
+#define FLD(f) abuf->fields.sfmt_move_c_sprv10_p9.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 6);