sim: sim-close: unify sim_close logic

[external/binutils.git] / sim / cris / crisv32f.c

diff --git a/sim/cris/crisv32f.c b/sim/cris/crisv32f.c
index d1d5fc9..dabd8b3 100644 (file)
--- a/sim/cris/crisv32f.c
+++ b/sim/cris/crisv32f.c
@@ -1,22 +1,21 @@
 /* CRIS v32 simulator support code
-   Copyright (C) 2004, 2005 Free Software Foundation, Inc.
+   Copyright (C) 2004-2015 Free Software Foundation, Inc.
    Contributed by Axis Communications.
 
 This file is part of the GNU simulators.
 
 This program is free software; you can redistribute it and/or modify
 it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
+the Free Software Foundation; either version 3 of the License, or
+(at your option) any later version.
 
 This program is distributed in the hope that it will be useful,
 but WITHOUT ANY WARRANTY; without even the implied warranty of
 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 GNU General Public License for more details.
 
-You should have received a copy of the GNU General Public License along
-with this program; if not, write to the Free Software Foundation, Inc.,
-59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+You should have received a copy of the GNU General Public License
+along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
 
 /* The infrastructure is based on that of i960.c.  */
 
@@ -29,6 +28,7 @@ with this program; if not, write to the Free Software Foundation, Inc.,
 #define SPECIFIC_U_MEM_FN
 #define SPECIFIC_U_MOVEM_FN
 #define BASENUM 32
+#define CRIS_TLS_REGISTER 2
 #include "cris-tmpl.c"
 
 #if WITH_PROFILE_MODEL_P
@@ -556,3 +556,73 @@ MY (XCONCAT3 (f_model_crisv,BASENUM,
 }
 
 #endif /* WITH_PROFILE_MODEL_P */
+
+int
+MY (deliver_interrupt) (SIM_CPU *current_cpu,
+                       enum cris_interrupt_type type,
+                       unsigned int vec)
+{
+  unsigned32 old_ccs, shifted_ccs, new_ccs;
+  unsigned char entryaddr_le[4];
+  int was_user;
+  SIM_DESC sd = CPU_STATE (current_cpu);
+  unsigned32 entryaddr;
+
+  /* We haven't implemented other interrupt-types yet.  */
+  if (type != CRIS_INT_INT)
+    abort ();
+
+  /* We're called outside of branch delay slots etc, so we don't check
+     for that.  */
+  if (!GET_H_IBIT_V32 ())
+    return 0;
+
+  old_ccs = GET_H_SR_V32 (H_SR_CCS);
+  shifted_ccs = (old_ccs << 10) & ((1 << 30) - 1);
+
+  /* The M bit is handled by code below and the M bit setter function, but
+     we need to preserve the Q bit.  */
+  new_ccs = shifted_ccs | (old_ccs & (unsigned32) 0x80000000UL);
+  was_user = GET_H_UBIT_V32 ();
+
+  /* We need to force kernel mode since the setter method doesn't allow
+     it.  Then we can use setter methods at will, since they then
+     recognize that we're in kernel mode.  */
+  CPU (h_ubit_v32) = 0;
+
+  SET_H_SR (H_SR_CCS, new_ccs);
+
+  if (was_user)
+    {
+      /* These methods require that user mode is unset.  */
+      SET_H_SR (H_SR_USP, GET_H_GR (H_GR_SP));
+      SET_H_GR (H_GR_SP, GET_H_KERNEL_SP ());
+    }
+
+  /* ERP setting is simplified by not taking interrupts in delay-slots
+     or when halting.  */
+  /* For all other exceptions than guru and NMI, store the return
+     address in ERP and set EXS and EXD here.  */
+  SET_H_SR (H_SR_ERP, GET_H_PC ());
+
+  /* Simplified by not having exception types (fault indications).  */
+  SET_H_SR_V32 (H_SR_EXS, (vec * 256));
+  SET_H_SR_V32 (H_SR_EDA, 0);
+
+  if (sim_core_read_buffer (sd,
+                           current_cpu,
+                           read_map, entryaddr_le,
+                           GET_H_SR (H_SR_EBP) + vec * 4, 4) == 0)
+    {
+      /* Nothing to do actually; either abort or send a signal.  */
+      sim_core_signal (sd, current_cpu, CPU_PC_GET (current_cpu), 0, 4,
+                      GET_H_SR (H_SR_EBP) + vec * 4,
+                      read_transfer, sim_core_unmapped_signal);
+      return 0;
+    }
+
+  entryaddr = bfd_getl32 (entryaddr_le);
+  SET_H_PC (entryaddr);
+
+  return 1;
+}