radeon_ms: add hang debuging helper functions

[profile/ivi/libdrm.git] / shared-core / radeon_ms_cp.c

diff --git a/shared-core/radeon_ms_cp.c b/shared-core/radeon_ms_cp.c
index c01769b..7b26c0b 100644 (file)
--- a/shared-core/radeon_ms_cp.c
+++ b/shared-core/radeon_ms_cp.c
@@ -156,7 +156,7 @@ int radeon_ms_cp_init(struct drm_device *dev)
                        dev_priv->ring_buffer_object->mem.num_pages,
                        &dev_priv->ring_buffer_map);
        if (ret) {
-               DRM_ERROR("[radeon_ms] error mapping ring buffer: %d\n", ret);
+               DRM_INFO("[radeon_ms] error mapping ring buffer: %d\n", ret);
                return ret;
        }
        dev_priv->ring_buffer = dev_priv->ring_buffer_map.virtual; 
@@ -275,15 +275,32 @@ void radeon_ms_cp_save(struct drm_device *dev, struct radeon_state *state)
 void radeon_ms_cp_stop(struct drm_device *dev)
 {
        struct drm_radeon_private *dev_priv = dev->dev_private;
+       uint32_t rbbm_status, rbbm_status_cp_mask;
 
-       MMIO_W(CP_CSQ_CNTL, REG_S(CP_CSQ_CNTL, CSQ_MODE,
-                               CSQ_MODE__CSQ_PRIDIS_INDDIS));
+       dev_priv->cp_ready = 0;
+       MMIO_W(CP_CSQ_CNTL, 0);
+       MMIO_R(CP_CSQ_CNTL);
+       MMIO_W(CP_CSQ_MODE, 0);
+       MMIO_R(CP_CSQ_MODE);
+       MMIO_W(RBBM_SOFT_RESET, RBBM_SOFT_RESET__SOFT_RESET_CP);
+       MMIO_R(RBBM_SOFT_RESET);
+       MMIO_W(RBBM_SOFT_RESET, 0);
+       MMIO_R(RBBM_SOFT_RESET);
+       rbbm_status = MMIO_R(RBBM_STATUS);
+       rbbm_status_cp_mask = (RBBM_STATUS__CPRQ_ON_RBB |
+                              RBBM_STATUS__CPRQ_IN_RTBUF |
+                              RBBM_STATUS__CP_CMDSTRM_BUSY);
+       if (rbbm_status & rbbm_status_cp_mask) {
+               DRM_INFO("[radeon_ms] cp busy (RBBM_STATUS: 0x%08X "
+                        "RBBM_STATUS(cp_mask): 0x%08X)\n", rbbm_status,
+                        rbbm_status_cp_mask);
+       }
        MMIO_W(CP_RB_CNTL, CP_RB_CNTL__RB_RPTR_WR_ENA);
        MMIO_W(CP_RB_RPTR_WR, 0);
        MMIO_W(CP_RB_WPTR, 0);
        DRM_UDELAY(5);
        dev_priv->ring_wptr = dev_priv->ring_rptr = MMIO_R(CP_RB_RPTR);
-       MMIO_W(CP_RB_WPTR, dev_priv->ring_wptr);
+       MMIO_W(CP_RB_CNTL, 0);
 }
 
 int radeon_ms_cp_wait(struct drm_device *dev, int n)
@@ -332,6 +349,7 @@ int radeon_ms_ring_emit(struct drm_device *dev, uint32_t *cmd, uint32_t count)
        dev_priv->ring_free -= count;
        for (i = 0; i < count; i++) {
                dev_priv->ring_buffer[dev_priv->ring_wptr] = cmd[i];
+               DRM_INFO("ring[%d] = 0x%08X\n", dev_priv->ring_wptr, cmd[i]);
                dev_priv->ring_wptr++;
                dev_priv->ring_wptr &= dev_priv->ring_mask;
        }
@@ -343,3 +361,28 @@ int radeon_ms_ring_emit(struct drm_device *dev, uint32_t *cmd, uint32_t count)
        spin_unlock(&ring_lock);
        return 0;
 }
+
+int radeon_ms_resetcp(struct drm_device *dev, void *data,
+                     struct drm_file *file_priv)
+{
+       struct drm_radeon_private *dev_priv = dev->dev_private;
+       int i;
+
+       DRM_INFO("[radeon_ms]--------------------------------------------\n");
+
+       /* reset VAP */
+       DRM_INFO("[radeon_ms] status before VAP : RBBM_STATUS: 0x%08X\n",
+                MMIO_R(RBBM_STATUS));
+       MMIO_W(RBBM_SOFT_RESET, RBBM_SOFT_RESET__SOFT_RESET_VAP);
+       MMIO_R(RBBM_SOFT_RESET);
+       MMIO_W(RBBM_SOFT_RESET, 0);
+       MMIO_R(RBBM_SOFT_RESET);
+       for (i = 0; i < 100; i++) {
+               DRM_UDELAY(100);
+       }
+       DRM_INFO("[radeon_ms] status after VAP  : RBBM_STATUS: 0x%08X\n",
+                MMIO_R(RBBM_STATUS));
+
+       DRM_INFO("[radeon_ms]--------------------------------------------\n");
+       return 0;
+}