#define DRIVER_DESC "nVidia Riva/TNT/GeForce"
#define DRIVER_DATE "20060213"
-#define DRIVER_MAJOR 1
+#define DRIVER_MAJOR 0
#define DRIVER_MINOR 0
-#define DRIVER_PATCHLEVEL 0
+#define DRIVER_PATCHLEVEL 6
#define NOUVEAU_FAMILY 0x0000FFFF
#define NOUVEAU_FLAGS 0xFFFF0000
#include "nouveau_drm.h"
#include "nouveau_reg.h"
+struct mem_block {
+ struct mem_block *next;
+ struct mem_block *prev;
+ uint64_t start;
+ uint64_t size;
+ DRMFILE filp; /* 0: free, -1: heap, other: real files */
+ int flags;
+ drm_local_map_t *map;
+};
+
enum nouveau_flags {
NV_NFORCE =0x10000000,
NV_NFORCE2 =0x20000000
{
struct nouveau_object *next;
struct nouveau_object *prev;
+ int channel;
+
+ struct mem_block *instance;
+ uint32_t ht_loc;
uint32_t handle;
int class;
int engine;
- uint32_t instance;
- uint32_t ht_loc;
};
-#define NV_DMA_TARGET_VIDMEM 0
-#define NV_DMA_TARGET_PCI 2
-#define NV_DMA_TARGET_AGP 3
struct nouveau_fifo
{
int used;
drm_local_map_t *map;
/* mapping of the regs controling the fifo */
drm_local_map_t *regs;
+ /* dma object for the command buffer itself */
+ struct mem_block *cmdbuf_mem;
+ struct nouveau_object *cmdbuf_obj;
+ uint32_t pushbuf_base;
+ /* PGRAPH context, for cards that keep it in RAMIN */
+ struct mem_block *ramin_grctx;
/* objects belonging to this fifo */
struct nouveau_object *objs;
-};
-
-struct nouveau_object_store
-{
- int ht_bits;
- int ht_size;
- int ht_base;
-
- uint32_t *inst_bmap;
- uint32_t first_instance;
- int num_instance;
- int free_instance;
-};
-struct mem_block {
- struct mem_block *next;
- struct mem_block *prev;
- uint64_t start;
- uint64_t size;
- DRMFILE filp; /* 0: free, -1: heap, other: real files */
- int flags;
- drm_local_map_t *map;
+ /* XXX dynamic alloc ? */
+ uint32_t pgraph_ctx [340];
};
struct nouveau_config {
} cmdbuf;
};
+typedef struct nouveau_engine_func {
+ struct {
+ int (*init)(drm_device_t *dev);
+ void (*takedown)(drm_device_t *dev);
+ } mc;
+
+ struct {
+ int (*init)(drm_device_t *dev);
+ void (*takedown)(drm_device_t *dev);
+ } timer;
+
+ struct {
+ int (*init)(drm_device_t *dev);
+ void (*takedown)(drm_device_t *dev);
+ } fb;
+
+ struct {
+ int (*init)(drm_device_t *);
+ void (*takedown)(drm_device_t *);
+
+ int (*create_context)(drm_device_t *, int channel);
+ void (*destroy_context)(drm_device_t *, int channel);
+ int (*load_context)(drm_device_t *, int channel);
+ int (*save_context)(drm_device_t *, int channel);
+ } graph;
+
+ struct {
+ int (*init)(drm_device_t *);
+ void (*takedown)(drm_device_t *);
+
+ int (*create_context)(drm_device_t *, int channel);
+ void (*destroy_context)(drm_device_t *, int channel);
+ int (*load_context)(drm_device_t *, int channel);
+ int (*save_context)(drm_device_t *, int channel);
+ } fifo;
+} nouveau_engine_func_t;
+
typedef struct drm_nouveau_private {
/* the card type, takes NV_* as values */
int card_type;
+ /* exact chipset, derived from NV_PMC_BOOT_0 */
+ int chipset;
int flags;
drm_local_map_t *mmio;
drm_local_map_t *fb;
+ drm_local_map_t *ramin; /* NV40 onwards */
- int cur_fifo;
+ int fifo_alloc_count;
+ struct nouveau_fifo fifos[NV_MAX_FIFO_NUMBER];
- struct nouveau_object *fb_obj;
- struct nouveau_object *cmdbuf_obj;
- int cmdbuf_ch_size;
- struct mem_block* cmdbuf_alloc;
+ struct nouveau_engine_func Engine;
- struct nouveau_fifo fifos[NV_MAX_FIFO_NUMBER];
- struct nouveau_object_store objs;
- /* RAMFC and RAMRO offsets */
+ /* RAMIN configuration, RAMFC, RAMHT and RAMRO offsets */
+ uint32_t ramin_size;
+ uint32_t ramht_offset;
+ uint32_t ramht_size;
+ uint32_t ramht_bits;
uint32_t ramfc_offset;
+ uint32_t ramfc_size;
uint32_t ramro_offset;
+ uint32_t ramro_size;
+
+ /* base physical adresses */
+ uint64_t fb_phys;
+ uint64_t fb_available_size;
+ uint64_t agp_phys;
+ uint64_t agp_available_size;
+
+ /* the mtrr covering the FB */
+ int fb_mtrr;
struct mem_block *agp_heap;
struct mem_block *fb_heap;
struct mem_block *fb_nomap_heap;
+ struct mem_block *ramin_heap;
+
+ /* context table pointed to be NV_PGRAPH_CHANNEL_CTX_TABLE (0x400780) */
+ uint32_t ctx_table_size;
+ struct mem_block *ctx_table;
struct nouveau_config config;
}
extern void nouveau_preclose(drm_device_t * dev, DRMFILE filp);
extern int nouveau_load(struct drm_device *dev, unsigned long flags);
extern int nouveau_firstopen(struct drm_device *dev);
+extern void nouveau_lastclose(struct drm_device *dev);
extern int nouveau_unload(struct drm_device *dev);
extern int nouveau_ioctl_getparam(DRM_IOCTL_ARGS);
extern int nouveau_ioctl_setparam(DRM_IOCTL_ARGS);
extern void nouveau_wait_for_idle(struct drm_device *dev);
+extern int nouveau_ioctl_card_init(DRM_IOCTL_ARGS);
/* nouveau_mem.c */
extern uint64_t nouveau_mem_fb_amount(struct drm_device *dev);
extern void nouveau_mem_free(struct drm_device* dev, struct mem_block*);
extern int nouveau_mem_init(struct drm_device *dev);
extern void nouveau_mem_close(struct drm_device *dev);
+extern int nouveau_instmem_init(struct drm_device *dev);
+extern struct mem_block* nouveau_instmem_alloc(struct drm_device *dev,
+ uint32_t size, uint32_t align);
+extern void nouveau_instmem_free(struct drm_device *dev,
+ struct mem_block *block);
+extern uint32_t nouveau_instmem_r32(drm_nouveau_private_t *dev_priv,
+ struct mem_block *mem, int index);
+extern void nouveau_instmem_w32(drm_nouveau_private_t *dev_priv,
+ struct mem_block *mem, int index,
+ uint32_t val);
/* nouveau_fifo.c */
+extern int nouveau_fifo_init(drm_device_t *dev);
extern int nouveau_fifo_number(drm_device_t *dev);
+extern int nouveau_fifo_ctx_size(drm_device_t *dev);
extern void nouveau_fifo_cleanup(drm_device_t *dev, DRMFILE filp);
-extern int nouveau_fifo_id_get(drm_device_t *dev, DRMFILE filp);
+extern int nouveau_fifo_owner(drm_device_t *dev, DRMFILE filp, int channel);
+extern void nouveau_fifo_free(drm_device_t *dev, int channel);
/* nouveau_object.c */
-extern void nouveau_hash_table_init(drm_device_t *dev);
-extern void nouveau_object_cleanup(drm_device_t *dev, DRMFILE filp);
-extern struct nouveau_object *nouveau_dma_object_create(drm_device_t *dev,
- uint32_t offset, uint32_t size, int access, uint32_t target);
+extern void nouveau_object_cleanup(drm_device_t *dev, int channel);
+extern struct nouveau_object *
+nouveau_object_gr_create(drm_device_t *dev, int channel, int class);
+extern struct nouveau_object *
+nouveau_object_dma_create(drm_device_t *dev, int channel, int class,
+ uint32_t offset, uint32_t size,
+ int access, int target);
+extern void nouveau_object_free(drm_device_t *dev, struct nouveau_object *obj);
extern int nouveau_ioctl_object_init(DRM_IOCTL_ARGS);
extern int nouveau_ioctl_dma_object_init(DRM_IOCTL_ARGS);
+extern uint32_t nouveau_chip_instance_get(drm_device_t *dev, struct mem_block *mem);
/* nouveau_irq.c */
extern irqreturn_t nouveau_irq_handler(DRM_IRQ_ARGS);
extern void nouveau_irq_postinstall(drm_device_t*);
extern void nouveau_irq_uninstall(drm_device_t*);
+/* nv04_fb.c */
+extern int nv04_fb_init(drm_device_t *dev);
+extern void nv04_fb_takedown(drm_device_t *dev);
+
+/* nv10_fb.c */
+extern int nv10_fb_init(drm_device_t *dev);
+extern void nv10_fb_takedown(drm_device_t *dev);
+
+/* nv40_fb.c */
+extern int nv40_fb_init(drm_device_t *dev);
+extern void nv40_fb_takedown(drm_device_t *dev);
+
+/* nv04_fifo.c */
+extern int nv04_fifo_create_context(drm_device_t *dev, int channel);
+extern void nv04_fifo_destroy_context(drm_device_t *dev, int channel);
+extern int nv04_fifo_load_context(drm_device_t *dev, int channel);
+extern int nv04_fifo_save_context(drm_device_t *dev, int channel);
+
+/* nv40_fifo.c */
+extern int nv40_fifo_create_context(drm_device_t *, int channel);
+extern void nv40_fifo_destroy_context(drm_device_t *, int channel);
+extern int nv40_fifo_load_context(drm_device_t *, int channel);
+extern int nv40_fifo_save_context(drm_device_t *, int channel);
+
+/* nv04_graph.c */
+extern void nouveau_nv04_context_switch(drm_device_t *dev);
+extern int nv04_graph_init(drm_device_t *dev);
+extern void nv04_graph_takedown(drm_device_t *dev);
+extern int nv04_graph_context_create(drm_device_t *dev, int channel);
+
+/* nv10_graph.c */
+extern void nouveau_nv10_context_switch(drm_device_t *dev);
+extern int nv10_graph_init(drm_device_t *dev);
+extern void nv10_graph_takedown(drm_device_t *dev);
+extern int nv10_graph_context_create(drm_device_t *dev, int channel);
+
+/* nv20_graph.c */
+extern void nouveau_nv20_context_switch(drm_device_t *dev);
+extern int nv20_graph_init(drm_device_t *dev);
+extern void nv20_graph_takedown(drm_device_t *dev);
+extern int nv20_graph_context_create(drm_device_t *dev, int channel);
+
+/* nv30_graph.c */
+extern int nv30_graph_init(drm_device_t *dev);
+extern void nv30_graph_takedown(drm_device_t *dev);
+extern int nv30_graph_context_create(drm_device_t *dev, int channel);
+
+/* nv40_graph.c */
+extern int nv40_graph_init(drm_device_t *);
+extern void nv40_graph_takedown(drm_device_t *);
+extern int nv40_graph_create_context(drm_device_t *, int channel);
+extern void nv40_graph_destroy_context(drm_device_t *, int channel);
+extern int nv40_graph_load_context(drm_device_t *, int channel);
+extern int nv40_graph_save_context(drm_device_t *, int channel);
+
+/* nv04_mc.c */
+extern int nv04_mc_init(drm_device_t *dev);
+extern void nv04_mc_takedown(drm_device_t *dev);
+
+/* nv40_mc.c */
+extern int nv40_mc_init(drm_device_t *dev);
+extern void nv40_mc_takedown(drm_device_t *dev);
+
+/* nv04_timer.c */
+extern int nv04_timer_init(drm_device_t *dev);
+extern void nv04_timer_takedown(drm_device_t *dev);
+
extern long nouveau_compat_ioctl(struct file *filp, unsigned int cmd,
unsigned long arg);
#define NV_WRITE(reg,val) DRM_WRITE32( dev_priv->mmio, (reg), (val) )
#endif
+#define INSTANCE_WR(mem,ofs,val) nouveau_instmem_w32(dev_priv,(mem),(ofs),(val))
+#define INSTANCE_RD(mem,ofs) nouveau_instmem_r32(dev_priv,(mem),(ofs))
+
#endif /* __NOUVEAU_DRV_H__ */
projects / platform / upstream / libdrm.git / blobdiff