#define DRIVER_MAJOR 0
#define DRIVER_MINOR 0
-#define DRIVER_PATCHLEVEL 10
+#define DRIVER_PATCHLEVEL 11
#define NOUVEAU_FAMILY 0x0000FFFF
#define NOUVEAU_FLAGS 0xFFFF0000
#include "nouveau_drm.h"
#include "nouveau_reg.h"
+#include "nouveau_bios.h"
+
+#define MAX_NUM_DCB_ENTRIES 16
struct mem_block {
struct mem_block *next;
struct mem_block *pushbuf_mem;
uint32_t pushbuf_base;
+ /* FIFO user control regs */
+ uint32_t user, user_size;
+ uint32_t put;
+ uint32_t get;
+ uint32_t ref_cnt;
+
/* Notifier memory */
struct mem_block *notifier_block;
struct mem_block *notifier_heap;
/* NV50 VM */
struct nouveau_gpuobj *vm_pd;
struct nouveau_gpuobj_ref *vm_gart_pt;
+ struct nouveau_gpuobj_ref *vm_vram_pt;
/* Objects */
struct nouveau_gpuobj_ref *ramin; /* Private instmem */
struct nouveau_fifo_engine fifo;
};
+#define NOUVEAU_MAX_CHANNEL_NR 128
struct drm_nouveau_private {
enum {
NOUVEAU_CARD_INIT_DOWN,
drm_local_map_t *ramin; /* NV40 onwards */
int fifo_alloc_count;
- struct nouveau_channel *fifos[NV_MAX_FIFO_NUMBER];
+ struct nouveau_channel *fifos[NOUVEAU_MAX_CHANNEL_NR];
struct nouveau_engine Engine;
struct nouveau_drm_channel channel;
unsigned long sg_handle;
} gart_info;
+ /* G8x global VRAM page table */
+ struct nouveau_gpuobj *vm_vram_pt;
+
/* the mtrr covering the FB */
int fb_mtrr;
struct nouveau_config config;
struct list_head gpuobj_list;
+
+ void *display_priv; /* internal modesetting */
+ void *kms_priv; /* related to public interface */
+
+ /* Hook these up to the "public interface" to accomodate a certain allocation style. */
+ /* This is to avoid polluting the internal interface. */
+ void *(*alloc_crtc) (struct drm_device *dev);
+ void *(*alloc_output) (struct drm_device *dev);
+ void *(*alloc_connector) (struct drm_device *dev);
+
+ void (*free_crtc) (void *crtc);
+ void (*free_output) (void *output);
+ void (*free_connector) (void *connector);
+
+ struct bios bios;
+
+ struct {
+ int entries;
+ struct dcb_entry entry[MAX_NUM_DCB_ENTRIES];
+ unsigned char i2c_read[MAX_NUM_DCB_ENTRIES];
+ unsigned char i2c_write[MAX_NUM_DCB_ENTRIES];
+ } dcb_table;
};
#define NOUVEAU_CHECK_INITIALISED_WITH_RETURN do { \
uint64_t size);
extern struct mem_block *nouveau_mem_alloc_block(struct mem_block *,
uint64_t size, int align2,
- struct drm_file *);
+ struct drm_file *, int tail);
extern void nouveau_mem_takedown(struct mem_block **heap);
extern void nouveau_mem_free_block(struct mem_block *);
+extern struct mem_block* find_block_by_handle(struct mem_block *heap, drm_handle_t handle);
extern uint64_t nouveau_mem_fb_amount(struct drm_device *);
extern void nouveau_mem_release(struct drm_file *, struct mem_block *heap);
extern int nouveau_ioctl_mem_alloc(struct drm_device *, void *data,
struct drm_file *);
extern int nouveau_ioctl_mem_free(struct drm_device *, void *data,
struct drm_file *);
+extern int nouveau_ioctl_mem_tile(struct drm_device *, void *data,
+ struct drm_file *);
extern struct mem_block* nouveau_mem_alloc(struct drm_device *,
int alignment, uint64_t size,
int flags, struct drm_file *);
/* nouveau_irq.c */
extern irqreturn_t nouveau_irq_handler(DRM_IRQ_ARGS);
extern void nouveau_irq_preinstall(struct drm_device *);
-extern void nouveau_irq_postinstall(struct drm_device *);
+extern int nouveau_irq_postinstall(struct drm_device *);
extern void nouveau_irq_uninstall(struct drm_device *);
/* nouveau_sgdma.c */