CONFIG_ARM_GIC_BASE_ADDRESS
CONFIG_AUTO_ZRELADDR
CONFIG_BOARDDIR
-CONFIG_DEFAULT
CONFIG_DFU_ALT
CONFIG_DFU_ALT_BOOT_EMMC
CONFIG_DFU_ALT_BOOT_SD
CONFIG_FEC_FIXED_SPEED
CONFIG_FEC_MXC_PHYADDR
CONFIG_FLASH_BR_PRELIM
-CONFIG_FLASH_CFI_LEGACY
CONFIG_FLASH_OR_PRELIM
CONFIG_FLASH_SECTOR_SIZE
CONFIG_FLASH_SHOW_PROGRESS
CONFIG_FLASH_VERIFY
CONFIG_FM_PLAT_CLK_DIV
CONFIG_FSL_CADMUS
-CONFIG_FSL_CORENET
CONFIG_FSL_CPLD
CONFIG_FSL_DEVICE_DISABLE
-CONFIG_FSL_DSPI1
CONFIG_FSL_ESDHC_PIN_MUX
CONFIG_FSL_FM_10GEC_REGULAR_NOTATION
CONFIG_FSL_IIM
CONFIG_FSL_ISBC_KEY_EXT
CONFIG_FSL_LBC
-CONFIG_FSL_MEMAC
-CONFIG_FSL_NGPIXIS
CONFIG_FSL_PMIC_BITLEN
CONFIG_FSL_PMIC_BUS
CONFIG_FSL_PMIC_CLK
CONFIG_FSL_SERDES
CONFIG_FSL_SERDES1
CONFIG_FSL_SERDES2
-CONFIG_FSL_SGMII_RISER
CONFIG_FTMAC100_BASE
CONFIG_FTRTC010_EXTCLK
CONFIG_FTRTC010_PCLK
CONFIG_GATEWAYIP
-CONFIG_GLOBAL_TIMER
CONFIG_GMII
CONFIG_G_DNL_THOR_PRODUCT_NUM
CONFIG_G_DNL_THOR_VENDOR_NUM
CONFIG_G_DNL_UMS_PRODUCT_NUM
CONFIG_G_DNL_UMS_VENDOR_NUM
CONFIG_HDMI_ENCODER_I2C_ADDR
-CONFIG_HIDE_LOGO_VERSION
CONFIG_HIKEY_GPIO
CONFIG_HOSTNAME
-CONFIG_HPS_ALTERAGRP_DBGATCLK
-CONFIG_HPS_ALTERAGRP_MAINCLK
-CONFIG_HPS_ALTERAGRP_MPUCLK
-CONFIG_HPS_CLK_CAN0_HZ
-CONFIG_HPS_CLK_CAN1_HZ
-CONFIG_HPS_CLK_EMAC0_HZ
-CONFIG_HPS_CLK_EMAC1_HZ
-CONFIG_HPS_CLK_F2S_PER_REF_HZ
-CONFIG_HPS_CLK_F2S_SDR_REF_HZ
-CONFIG_HPS_CLK_GPIODB_HZ
-CONFIG_HPS_CLK_L4_MP_HZ
-CONFIG_HPS_CLK_L4_SP_HZ
-CONFIG_HPS_CLK_MAINVCO_HZ
-CONFIG_HPS_CLK_NAND_HZ
-CONFIG_HPS_CLK_OSC1_HZ
-CONFIG_HPS_CLK_OSC2_HZ
-CONFIG_HPS_CLK_PERVCO_HZ
-CONFIG_HPS_CLK_QSPI_HZ
-CONFIG_HPS_CLK_SDMMC_HZ
-CONFIG_HPS_CLK_SDRVCO_HZ
-CONFIG_HPS_CLK_SPIM_HZ
-CONFIG_HPS_CLK_USBCLK_HZ
-CONFIG_HPS_DBCTRL_STAYOSC1
-CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH
-CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH
-CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH
-CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH
-CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT
-CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT
-CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK
-CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK
-CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP
-CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP
-CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT
-CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK
-CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK
-CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK
-CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK
-CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT
-CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT
-CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT
-CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK
-CONFIG_HPS_MAINPLLGRP_VCO_DENOM
-CONFIG_HPS_MAINPLLGRP_VCO_NUMER
-CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK
-CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK
-CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK
-CONFIG_HPS_PERPLLGRP_DIV_USBCLK
-CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT
-CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT
-CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK
-CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT
-CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT
-CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT
-CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT
-CONFIG_HPS_PERPLLGRP_SRC_NAND
-CONFIG_HPS_PERPLLGRP_SRC_QSPI
-CONFIG_HPS_PERPLLGRP_SRC_SDMMC
-CONFIG_HPS_PERPLLGRP_VCO_DENOM
-CONFIG_HPS_PERPLLGRP_VCO_NUMER
-CONFIG_HPS_PERPLLGRP_VCO_PSRC
-CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT
-CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE
-CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT
-CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE
-CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT
-CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE
-CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT
-CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE
-CONFIG_HPS_SDRPLLGRP_VCO_DENOM
-CONFIG_HPS_SDRPLLGRP_VCO_NUMER
-CONFIG_HPS_SDRPLLGRP_VCO_SSRC
-CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR
-CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP
-CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH
-CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP
-CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER
-CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN
-CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN
-CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN
-CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL
-CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE
-CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS
-CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN
-CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT
-CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH
-CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS
-CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS
-CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS
-CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS
-CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH
-CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH
-CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN
-CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ
-CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE
-CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL
-CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL
-CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL
-CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW
-CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC
-CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD
-CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD
-CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI
-CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP
-CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR
-CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR
-CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD
-CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD
-CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS
-CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC
-CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP
-CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT
-CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT
-CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC
-CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE
-CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST
-CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST_COMMAND_PORT_USED
-CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST_READ_PORT_USED
-CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST_WRITE_PORT_USED
-CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK
-CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES
-CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES
-CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0
-CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32
-CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0
-CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4
-CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36
-CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY
-CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0
-CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32
-CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64
-CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0
-CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32
-CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0
-CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14
-CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46
-CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0
-CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN
-CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP
-CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL
-CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA
-CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP
CONFIG_HSMMC2_8BIT
CONFIG_HWCONFIG
CONFIG_HW_ENV_SETTINGS
CONFIG_IRAM_END
CONFIG_IRAM_SIZE
CONFIG_IRAM_TOP
-CONFIG_KM_BOARD_EXTRA_ENV
CONFIG_KM_DEF_ARCH
CONFIG_KM_DEF_BOOT_ARGS_CPU
CONFIG_KM_DEF_ENV
CONFIG_KM_DEV_ENV_FLASH_BOOT_UBI
CONFIG_KM_ECC_MODE
CONFIG_KM_NEW_ENV
-CONFIG_KM_ROOTFSSIZE
CONFIG_KM_UBI_LINUX_MTD
CONFIG_KM_UBI_PARTITION_NAME_APP
CONFIG_KM_UBI_PARTITION_NAME_BOOT
CONFIG_KM_UBI_PART_BOOT_OPTS
CONFIG_KM_UIMAGE_NAME
-CONFIG_KM_UPDATE_UBOOT
CONFIG_KSNET_CPSW_NUM_PORTS
CONFIG_KSNET_MAC_ID_BASE
CONFIG_KSNET_MDIO_PHY_CONFIG_ENABLE
CONFIG_KSNET_SERDES_SGMII_BASE
CONFIG_L1_INIT_RAM
CONFIG_L2_CACHE
-CONFIG_LCD_ALIGNMENT
-CONFIG_LCD_MENU
-CONFIG_LD9040
CONFIG_LEGACY_BOOTCMD_ENV
-CONFIG_LOADS_ECHO
CONFIG_LOWPOWER_ADDR
CONFIG_LOWPOWER_FLAG
CONFIG_LPC32XX_HSUART
CONFIG_NEVER_ASSERT_ODT_TO_CPU
CONFIG_NOBQFMAN
CONFIG_NORBOOT
-CONFIG_NS16550_MIN_FUNCTIONS
CONFIG_NUM_DSP_CPUS
CONFIG_ODROID_REV_AIN
CONFIG_OTHBOOTARGS
CONFIG_RTC_DS1374
CONFIG_RTC_DS3231
CONFIG_RTC_MC13XXX
-CONFIG_RTC_MCFRRTC
CONFIG_RTC_MXS
CONFIG_RTC_PT7C4338
-CONFIG_SAMA5D3_LCD_BASE
CONFIG_SANDBOX_ARCH
CONFIG_SANDBOX_SDL
CONFIG_SANDBOX_SPI_MAX_BUS
CONFIG_SCIF_A
CONFIG_SCSI_DEV_LIST
CONFIG_SC_TIMER_CLK
-CONFIG_SDRAM_OFFSET_FOR_RT
CONFIG_SERIAL_BOOT
CONFIG_SERIAL_SOFTWARE_FIFO
CONFIG_SERVERIP
CONFIG_SETUP_INITRD_TAG
CONFIG_SET_DFU_ALT_BUF_LEN
-CONFIG_SH73A0
CONFIG_SH_ETHER_ALIGNE_SIZE
-CONFIG_SH_ETHER_BASE_ADDR
CONFIG_SH_ETHER_CACHE_INVALIDATE
CONFIG_SH_ETHER_CACHE_WRITEBACK
CONFIG_SH_ETHER_PHY_ADDR
CONFIG_SH_ETHER_USE_PORT
CONFIG_SH_GPIO_PFC
CONFIG_SH_QSPI_BASE
-CONFIG_SKIP_LOCAL_MAC_RANDOMIZATION
CONFIG_SLIC
-CONFIG_SMC91111
-CONFIG_SMC91111_BASE
-CONFIG_SMC91111_EXT_PHY
-CONFIG_SMC_USE_32_BIT
CONFIG_SMDK5420
CONFIG_SMP_PEN_ADDR
CONFIG_SMSC_LPC47M
CONFIG_SPI_FLASH_SIZE
CONFIG_SPI_HALF_DUPLEX
CONFIG_SPI_N25Q256A_RESET
+CONFIG_SPL_NS16550_MIN_FUNCTIONS
CONFIG_SRIO1
CONFIG_SRIO2
CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET
CONFIG_SYS_BMAN_SP_CINH_SIZE
CONFIG_SYS_BMAN_SWP_ISDR_REG
CONFIG_SYS_BOOTMAPSZ
-CONFIG_SYS_BOOT_BLOCK
CONFIG_SYS_CACHE_ACR0
CONFIG_SYS_CACHE_ACR1
CONFIG_SYS_CACHE_ACR2
CONFIG_SYS_CCSRBAR_PHYS_LOW
CONFIG_SYS_CLK
CONFIG_SYS_CLKTL_CBCDR
-CONFIG_SYS_CORE_SRAM
-CONFIG_SYS_CORE_SRAM_SIZE
CONFIG_SYS_CPLD_AMASK
CONFIG_SYS_CPLD_BASE
CONFIG_SYS_CPLD_BASE_PHYS
CONFIG_SYS_CPLD_FTIM1
CONFIG_SYS_CPLD_FTIM2
CONFIG_SYS_CPLD_FTIM3
-CONFIG_SYS_CPLD_SIZE
CONFIG_SYS_CPU_CLK
CONFIG_SYS_CS0_BASE
CONFIG_SYS_CS0_CTRL
CONFIG_SYS_DDR_CLK_CNTL
CONFIG_SYS_DDR_CLK_CONTROL
CONFIG_SYS_DDR_CLK_CTRL
-CONFIG_SYS_DDR_CLK_CTRL_667
-CONFIG_SYS_DDR_CLK_CTRL_800
CONFIG_SYS_DDR_CONFIG
CONFIG_SYS_DDR_CONFIG_2
-CONFIG_SYS_DDR_CONFIG_256
CONFIG_SYS_DDR_CONTROL
CONFIG_SYS_DDR_CONTROL_2
CONFIG_SYS_DDR_CS0_BNDS
CONFIG_SYS_DDR_INIT_ADDR
CONFIG_SYS_DDR_INIT_EXT_ADDR
CONFIG_SYS_DDR_INTERVAL
-CONFIG_SYS_DDR_INTERVAL_667
-CONFIG_SYS_DDR_INTERVAL_800
CONFIG_SYS_DDR_MODE
CONFIG_SYS_DDR_MODE2
CONFIG_SYS_DDR_MODE_1
-CONFIG_SYS_DDR_MODE_1_667
-CONFIG_SYS_DDR_MODE_1_800
CONFIG_SYS_DDR_MODE_2
-CONFIG_SYS_DDR_MODE_2_667
-CONFIG_SYS_DDR_MODE_2_800
CONFIG_SYS_DDR_MODE_CONTROL
CONFIG_SYS_DDR_RCW_1
CONFIG_SYS_DDR_RCW_2
CONFIG_SYS_DDR_SDRAM_CFG
CONFIG_SYS_DDR_SDRAM_CFG2
CONFIG_SYS_DDR_SDRAM_CLK_CNTL
-CONFIG_SYS_DDR_SIZE
CONFIG_SYS_DDR_SR_CNTR
CONFIG_SYS_DDR_TIMING_0
-CONFIG_SYS_DDR_TIMING_0_667
-CONFIG_SYS_DDR_TIMING_0_800
CONFIG_SYS_DDR_TIMING_1
-CONFIG_SYS_DDR_TIMING_1_667
-CONFIG_SYS_DDR_TIMING_1_800
CONFIG_SYS_DDR_TIMING_2
-CONFIG_SYS_DDR_TIMING_2_667
-CONFIG_SYS_DDR_TIMING_2_800
CONFIG_SYS_DDR_TIMING_3
-CONFIG_SYS_DDR_TIMING_3_667
-CONFIG_SYS_DDR_TIMING_3_800
CONFIG_SYS_DDR_TIMING_4
CONFIG_SYS_DDR_TIMING_5
CONFIG_SYS_DDR_WRLVL_CONTROL
-CONFIG_SYS_DDR_WRLVL_CONTROL_667
-CONFIG_SYS_DDR_WRLVL_CONTROL_800
CONFIG_SYS_DDR_ZQ_CONTROL
-CONFIG_SYS_DEBUG
-CONFIG_SYS_DEBUG_SERVER_FW_ADDR
-CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR
CONFIG_SYS_DIALOG_PMIC_I2C_ADDR
-CONFIG_SYS_DIRECT_FLASH_TFTP
CONFIG_SYS_DPAA_DCE
CONFIG_SYS_DPAA_FMAN
CONFIG_SYS_DPAA_PME
CONFIG_SYS_DPAA_RMAN
-CONFIG_SYS_DRAM_SIZE
CONFIG_SYS_DRAM_TEST
-CONFIG_SYS_DSPI_CTAR0
-CONFIG_SYS_DSPI_CTAR1
-CONFIG_SYS_DSPI_CTAR2
-CONFIG_SYS_DSPI_CTAR3
CONFIG_SYS_DV_NOR_BOOT_CFG
-CONFIG_SYS_EEPROM_BUS_NUM
-CONFIG_SYS_EEPROM_PAGE_WRITE_ENABLE
-CONFIG_SYS_EEPROM_WREN
-CONFIG_SYS_ENET_BD_BASE
CONFIG_SYS_ENV_SECT_SIZE
CONFIG_SYS_ETHOC_BASE
CONFIG_SYS_ETHOC_BUFFER_ADDR
CONFIG_SYS_EXCEPTION_VECTORS_HIGH
CONFIG_SYS_FAST_CLK
-CONFIG_SYS_FDT_PAD
-CONFIG_SYS_FECI2C
CONFIG_SYS_FEC_BUF_USE_SRAM
CONFIG_SYS_FLASH0
CONFIG_SYS_FLASH1
CONFIG_SYS_FLASH_BANKS_LIST
CONFIG_SYS_FLASH_BANKS_SIZES
CONFIG_SYS_FLASH_BASE
-CONFIG_SYS_FLASH_BASE0
-CONFIG_SYS_FLASH_BASE1
CONFIG_SYS_FLASH_BASE_PHYS
CONFIG_SYS_FLASH_BASE_PHYS_EARLY
-CONFIG_SYS_FLASH_BR_PRELIM
-CONFIG_SYS_FLASH_CFI_NONBLOCK
-CONFIG_SYS_FLASH_CHECKSUM
-CONFIG_SYS_FLASH_EMPTY_INFO
-CONFIG_SYS_FLASH_ERASE_TOUT
-CONFIG_SYS_FLASH_LOCK_TOUT
-CONFIG_SYS_FLASH_OR_PRELIM
CONFIG_SYS_FLASH_PARMSECT_SZ
-CONFIG_SYS_FLASH_QUIET_TEST
-CONFIG_SYS_FLASH_SECT_SIZE
-CONFIG_SYS_FLASH_SECT_SZ
CONFIG_SYS_FLASH_SIZE
-CONFIG_SYS_FLASH_UNLOCK_TOUT
-CONFIG_SYS_FLASH_WRITE_TOUT
CONFIG_SYS_FM1_10GEC1_PHY_ADDR
CONFIG_SYS_FM1_CLK
CONFIG_SYS_FM1_DTSEC1_PHY_ADDR
CONFIG_SYS_FM1_DTSEC5_PHY_ADDR
CONFIG_SYS_FM1_QSGMII11_PHY_ADDR
CONFIG_SYS_FM1_QSGMII21_PHY_ADDR
-CONFIG_SYS_FM2_10GEC1_PHY_ADDR
CONFIG_SYS_FM2_CLK
-CONFIG_SYS_FM2_DTSEC1_PHY_ADDR
-CONFIG_SYS_FM2_DTSEC2_PHY_ADDR
-CONFIG_SYS_FM2_DTSEC3_PHY_ADDR
-CONFIG_SYS_FM2_DTSEC4_PHY_ADDR
-CONFIG_SYS_FMAN_V3
CONFIG_SYS_FM_MURAM_SIZE
-CONFIG_SYS_FPGAREG_DATE
CONFIG_SYS_FPGAREG_DIPSW
CONFIG_SYS_FPGAREG_FREQ
CONFIG_SYS_FPGAREG_RESET
CONFIG_SYS_FPGA_FTIM3
CONFIG_SYS_FPGA_SIZE
CONFIG_SYS_FPGA_WAIT
-CONFIG_SYS_FSL_BMAN_ADDR
-CONFIG_SYS_FSL_BMAN_OFFSET
-CONFIG_SYS_FSL_CCSR_GUR_BE
-CONFIG_SYS_FSL_CCSR_GUR_LE
-CONFIG_SYS_FSL_CCSR_SCFG_BE
-CONFIG_SYS_FSL_CCSR_SCFG_LE
-CONFIG_SYS_FSL_CH3_CLK_CTRL_ADDR
-CONFIG_SYS_FSL_CH3_CLK_GRPA_ADDR
-CONFIG_SYS_FSL_CH3_CLK_GRPB_ADDR
-CONFIG_SYS_FSL_CLK_ADDR
-CONFIG_SYS_FSL_CLUSTER_1_L2
-CONFIG_SYS_FSL_CLUSTER_1_L2_OFFSET
-CONFIG_SYS_FSL_CLUSTER_CLOCKS
-CONFIG_SYS_FSL_CORENET_CCM_ADDR
-CONFIG_SYS_FSL_CORENET_CCM_OFFSET
-CONFIG_SYS_FSL_CORENET_CLK_ADDR
-CONFIG_SYS_FSL_CORENET_CLK_OFFSET
-CONFIG_SYS_FSL_CORENET_PMAN
-CONFIG_SYS_FSL_CORENET_PMAN1_OFFSET
-CONFIG_SYS_FSL_CORENET_PMAN2_OFFSET
-CONFIG_SYS_FSL_CORENET_PMAN3_OFFSET
-CONFIG_SYS_FSL_CORENET_PME_ADDR
-CONFIG_SYS_FSL_CORENET_PME_OFFSET
-CONFIG_SYS_FSL_CORENET_RCPM_ADDR
-CONFIG_SYS_FSL_CORENET_RCPM_OFFSET
-CONFIG_SYS_FSL_CORENET_RMAN_ADDR
-CONFIG_SYS_FSL_CORENET_RMAN_OFFSET
-CONFIG_SYS_FSL_CORENET_SERDES2_ADDR
-CONFIG_SYS_FSL_CORENET_SERDES2_OFFSET
-CONFIG_SYS_FSL_CORENET_SERDES3_ADDR
-CONFIG_SYS_FSL_CORENET_SERDES3_OFFSET
-CONFIG_SYS_FSL_CORENET_SERDES4_ADDR
-CONFIG_SYS_FSL_CORENET_SERDES4_OFFSET
-CONFIG_SYS_FSL_CORENET_SERDES_ADDR
-CONFIG_SYS_FSL_CORENET_SERDES_OFFSET
-CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY
-CONFIG_SYS_FSL_CORES_PER_CLUSTER
-CONFIG_SYS_FSL_CPC_ADDR
-CONFIG_SYS_FSL_CPC_OFFSET
-CONFIG_SYS_FSL_CSU_ADDR
-CONFIG_SYS_FSL_DCSR_DDR2_ADDR
-CONFIG_SYS_FSL_DCSR_DDR3_ADDR
-CONFIG_SYS_FSL_DCSR_DDR_ADDR
-CONFIG_SYS_FSL_DDR2_ADDR
-CONFIG_SYS_FSL_DDR3_ADDR
-CONFIG_SYS_FSL_DDR_ADDR
-CONFIG_SYS_FSL_DDR_INTLV_256B
-CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS
-CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY
-CONFIG_SYS_FSL_DSPI_BE
-CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT
-CONFIG_SYS_FSL_DSP_CCSR_DDR_ADDR
-CONFIG_SYS_FSL_DSP_CCSR_DDR_OFFSET
-CONFIG_SYS_FSL_DSP_DDR_ADDR
-CONFIG_SYS_FSL_DSP_M2_RAM_ADDR
-CONFIG_SYS_FSL_DSP_M3_RAM_ADDR
-CONFIG_SYS_FSL_ERRATUM_A008751
-CONFIG_SYS_FSL_ESDHC_ADDR
-CONFIG_SYS_FSL_ESDHC_BE
-CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
-CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE
-CONFIG_SYS_FSL_ESDHC_LE
-CONFIG_SYS_FSL_ESDHC_NUM
-CONFIG_SYS_FSL_ESDHC_P1010_BROKEN_SDCLK
-CONFIG_SYS_FSL_FM
-CONFIG_SYS_FSL_FM1_ADDR
-CONFIG_SYS_FSL_FM1_DTSEC1_ADDR
-CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET
-CONFIG_SYS_FSL_FM1_OFFSET
-CONFIG_SYS_FSL_FM1_RX0_10G_OFFSET
-CONFIG_SYS_FSL_FM1_RX0_1G_OFFSET
-CONFIG_SYS_FSL_FM1_RX1_10G_OFFSET
-CONFIG_SYS_FSL_FM1_RX1_1G_OFFSET
-CONFIG_SYS_FSL_FM1_RX2_1G_OFFSET
-CONFIG_SYS_FSL_FM1_RX3_1G_OFFSET
-CONFIG_SYS_FSL_FM1_RX4_1G_OFFSET
-CONFIG_SYS_FSL_FM1_RX5_1G_OFFSET
-CONFIG_SYS_FSL_FM2_ADDR
-CONFIG_SYS_FSL_FM2_OFFSET
-CONFIG_SYS_FSL_FM2_RX0_10G_OFFSET
-CONFIG_SYS_FSL_FM2_RX0_1G_OFFSET
-CONFIG_SYS_FSL_FM2_RX1_10G_OFFSET
-CONFIG_SYS_FSL_FM2_RX1_1G_OFFSET
-CONFIG_SYS_FSL_FM2_RX2_1G_OFFSET
-CONFIG_SYS_FSL_FM2_RX3_1G_OFFSET
-CONFIG_SYS_FSL_FM2_RX4_1G_OFFSET
-CONFIG_SYS_FSL_FM2_RX5_1G_OFFSET
-CONFIG_SYS_FSL_GUTS_ADDR
-CONFIG_SYS_FSL_IFC_BE
-CONFIG_SYS_FSL_IFC_LE
-CONFIG_SYS_FSL_ISBC_VER
-CONFIG_SYS_FSL_JR0_ADDR
-CONFIG_SYS_FSL_JR0_OFFSET
-CONFIG_SYS_FSL_LS1_CLK_ADDR
-CONFIG_SYS_FSL_LSCH3_SERDES_ADDR
-CONFIG_SYS_FSL_MAX_NUM_OF_SEC
-CONFIG_SYS_FSL_NUM_CC_PLL
-CONFIG_SYS_FSL_NUM_CC_PLLS
-CONFIG_SYS_FSL_OCRAM_BASE
-CONFIG_SYS_FSL_OCRAM_SIZE
-CONFIG_SYS_FSL_OTHER_DDR_NUM_CTRLS
-CONFIG_SYS_FSL_PAMU_OFFSET
-CONFIG_SYS_FSL_PCIE_COMPAT
-CONFIG_SYS_FSL_PEX_LUT_BE
-CONFIG_SYS_FSL_PEX_LUT_LE
-CONFIG_SYS_FSL_PMIC_I2C_ADDR
-CONFIG_SYS_FSL_PMU_ADDR
-CONFIG_SYS_FSL_PMU_CLTBENR
-CONFIG_SYS_FSL_QMAN_ADDR
-CONFIG_SYS_FSL_QMAN_OFFSET
-CONFIG_SYS_FSL_QMAN_V3
-CONFIG_SYS_FSL_QSPI_BASE
-CONFIG_SYS_FSL_QSPI_LE
-CONFIG_SYS_FSL_RAID_ENGINE
-CONFIG_SYS_FSL_RAID_ENGINE_ADDR
-CONFIG_SYS_FSL_RAID_ENGINE_OFFSET
-CONFIG_SYS_FSL_RCPM_ADDR
-CONFIG_SYS_FSL_RMU
-CONFIG_SYS_FSL_RST_ADDR
-CONFIG_SYS_FSL_SCFG_ADDR
-CONFIG_SYS_FSL_SCFG_IODSECR1_ADDR
-CONFIG_SYS_FSL_SCFG_IODSECR1_OFFSET
-CONFIG_SYS_FSL_SCFG_OFFSET
-CONFIG_SYS_FSL_SCFG_PIXCLKCR_OFFSET
-CONFIG_SYS_FSL_SCFG_PIXCLK_ADDR
-CONFIG_SYS_FSL_SEC_ADDR
-CONFIG_SYS_FSL_SEC_IDX_OFFSET
-CONFIG_SYS_FSL_SEC_OFFSET
-CONFIG_SYS_FSL_SERDES
-CONFIG_SYS_FSL_SERDES_ADDR
-CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
-CONFIG_SYS_FSL_SRDS_3
-CONFIG_SYS_FSL_SRDS_4
-CONFIG_SYS_FSL_SRDS_NUM_PLLS
-CONFIG_SYS_FSL_SRIO_ADDR
-CONFIG_SYS_FSL_SRIO_IB_WIN_NUM
-CONFIG_SYS_FSL_SRIO_LIODN
-CONFIG_SYS_FSL_SRIO_MAX_PORTS
-CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM
-CONFIG_SYS_FSL_SRIO_OB_WIN_NUM
-CONFIG_SYS_FSL_SRIO_OFFSET
-CONFIG_SYS_FSL_TBCLK_DIV
-CONFIG_SYS_FSL_TIMER_ADDR
-CONFIG_SYS_FSL_USB1_PHY_ENABLE
-CONFIG_SYS_FSL_USB2_PHY_ENABLE
-CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
-CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
-CONFIG_SYS_FSL_USDHC_NUM
-CONFIG_SYS_FSL_WDOG_BE
-CONFIG_SYS_FSL_WRIOP1_ADDR
-CONFIG_SYS_FSL_WRIOP1_MDIO1
-CONFIG_SYS_FSL_WRIOP1_MDIO2
-CONFIG_SYS_GP1DIR
-CONFIG_SYS_GP1ODR
-CONFIG_SYS_GP2DIR
-CONFIG_SYS_GP2ODR
CONFIG_SYS_GPIO1_EN
CONFIG_SYS_GPIO1_FUNC
CONFIG_SYS_GPIO1_LED
CONFIG_SYS_GPIO_FUNC
CONFIG_SYS_GPIO_OUT
CONFIG_SYS_GPR1
-CONFIG_SYS_HALT_BEFOR_RAM_JUMP
-CONFIG_SYS_HMI_BASE
CONFIG_SYS_HZ_CLOCK
CONFIG_SYS_I2C_BUSES
-CONFIG_SYS_I2C_DVI_ADDR
-CONFIG_SYS_I2C_DVI_BUS_NUM
-CONFIG_SYS_I2C_EEPROM_CCID
-CONFIG_SYS_I2C_EEPROM_NXID
-CONFIG_SYS_I2C_EEPROM_PAGE_WRITE_BITS
-CONFIG_SYS_I2C_EEPROM_PAGE_WRITE_DELAY_MS
CONFIG_SYS_I2C_EXPANDER_ADDR
CONFIG_SYS_I2C_FPGA_ADDR
CONFIG_SYS_I2C_G762_ADDR
CONFIG_SYS_I2C_IFDR_DIV
-CONFIG_SYS_I2C_INIT_BOARD
-CONFIG_SYS_I2C_LDI_ADDR
CONFIG_SYS_I2C_MAX_HOPS
CONFIG_SYS_I2C_NOPROBES
CONFIG_SYS_I2C_PCA953X_ADDR
CONFIG_SYS_INIT_L2_END
CONFIG_SYS_INIT_L3_ADDR
CONFIG_SYS_INIT_L3_ADDR_PHYS
-CONFIG_SYS_INIT_L3_END
CONFIG_SYS_INIT_L3_VADDR
CONFIG_SYS_INIT_RAM_ADDR
CONFIG_SYS_INIT_RAM_ADDR_PHYS
CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH
CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW
CONFIG_SYS_INIT_RAM_CTRL
-CONFIG_SYS_INIT_RAM_LOCK
CONFIG_SYS_INIT_RAM_SIZE
CONFIG_SYS_INIT_SP_OFFSET
-CONFIG_SYS_INTERLAKEN
CONFIG_SYS_INT_FLASH_BASE
CONFIG_SYS_INT_FLASH_ENABLE
CONFIG_SYS_IO_BASE
-CONFIG_SYS_ISA_IO
-CONFIG_SYS_ISA_IO_BASE_ADDRESS
-CONFIG_SYS_JFFS2_FIRST_BANK
-CONFIG_SYS_JFFS2_FIRST_SECTOR
-CONFIG_SYS_JFFS2_NUM_BANKS
CONFIG_SYS_KMBEC_FPGA_BASE
CONFIG_SYS_KMBEC_FPGA_SIZE
-CONFIG_SYS_L2_PL310
-CONFIG_SYS_L2_SIZE
-CONFIG_SYS_L3_SIZE
CONFIG_SYS_LATCH_ADDR
CONFIG_SYS_LBC_ADDR
-CONFIG_SYS_LBC_CACHE_BASE
CONFIG_SYS_LBC_FLASH_BASE
CONFIG_SYS_LBC_LBCR
CONFIG_SYS_LBC_LCRR
CONFIG_SYS_LBC_SDRAM_SIZE
CONFIG_SYS_LDB_CLOCK
CONFIG_SYS_LIME_BASE
-CONFIG_SYS_LIME_SIZE
-CONFIG_SYS_LOADS_BAUD_CHANGE
CONFIG_SYS_LOW
CONFIG_SYS_LOWMEM_BASE
CONFIG_SYS_LPAE_SDRAM_BASE
CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE
CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET
CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET
-CONFIG_SYS_M41T11_BASE_YEAR
CONFIG_SYS_MAIN_PWR_ON
-CONFIG_SYS_MAMR
CONFIG_SYS_MASTER_CLOCK
CONFIG_SYS_MATRIX_EBI0CSA_VAL
CONFIG_SYS_MATRIX_EBICSA_VAL
-CONFIG_SYS_MAX_FLASH_SECT
CONFIG_SYS_MAX_I2C_BUS
CONFIG_SYS_MAX_NAND_CHIPS
-CONFIG_SYS_MAX_NAND_DEVICE
CONFIG_SYS_MBAR
CONFIG_SYS_MBAR2
-CONFIG_SYS_MCFRRTC_BASE
CONFIG_SYS_MCKR
CONFIG_SYS_MCKR1_VAL
CONFIG_SYS_MCKR2_VAL
CONFIG_SYS_MCKR_CSS
CONFIG_SYS_MDIO1_OFFSET
-CONFIG_SYS_MEMAC_LITTLE_ENDIAN
CONFIG_SYS_MEMORY_BASE
-CONFIG_SYS_MEMORY_SIZE
CONFIG_SYS_MEM_RESERVE_SECURE
-CONFIG_SYS_MEM_SIZE
CONFIG_SYS_MFD
-CONFIG_SYS_MHZ
-CONFIG_SYS_MIPS_TIMER_FREQ
CONFIG_SYS_MMC_CD_PIN
CONFIG_SYS_MMC_CLK_OD
-CONFIG_SYS_MMC_MAX_BLK_COUNT
-CONFIG_SYS_MMC_MAX_DEVICE
CONFIG_SYS_MMC_U_BOOT_DST
CONFIG_SYS_MMC_U_BOOT_OFFS
CONFIG_SYS_MMC_U_BOOT_SIZE
CONFIG_SYS_MMC_U_BOOT_START
-CONFIG_SYS_MONITOR_LEN
-CONFIG_SYS_MONITOR_SEC
CONFIG_SYS_MOR_VAL
-CONFIG_SYS_MPC83xx_DMA_ADDR
-CONFIG_SYS_MPC83xx_DMA_OFFSET
-CONFIG_SYS_MPC83xx_ESDHC_ADDR
-CONFIG_SYS_MPC83xx_ESDHC_OFFSET
-CONFIG_SYS_MPC85xx_DMA
-CONFIG_SYS_MPC85xx_DMA1_OFFSET
-CONFIG_SYS_MPC85xx_DMA2_OFFSET
-CONFIG_SYS_MPC85xx_DMA3_OFFSET
-CONFIG_SYS_MPC85xx_DMA_ADDR
-CONFIG_SYS_MPC85xx_DMA_OFFSET
-CONFIG_SYS_MPC85xx_ECM_ADDR
-CONFIG_SYS_MPC85xx_ECM_OFFSET
-CONFIG_SYS_MPC85xx_ESDHC_ADDR
-CONFIG_SYS_MPC85xx_ESDHC_OFFSET
-CONFIG_SYS_MPC85xx_ESPI_ADDR
-CONFIG_SYS_MPC85xx_ESPI_OFFSET
-CONFIG_SYS_MPC85xx_GPIO_ADDR
-CONFIG_SYS_MPC85xx_GPIO_OFFSET
-CONFIG_SYS_MPC85xx_GUTS_ADDR
-CONFIG_SYS_MPC85xx_GUTS_OFFSET
-CONFIG_SYS_MPC85xx_IFC_OFFSET
-CONFIG_SYS_MPC85xx_L2_ADDR
-CONFIG_SYS_MPC85xx_L2_OFFSET
-CONFIG_SYS_MPC85xx_LBC_OFFSET
-CONFIG_SYS_MPC85xx_PCI1_OFFSET
-CONFIG_SYS_MPC85xx_PCI2_OFFSET
-CONFIG_SYS_MPC85xx_PCIE
-CONFIG_SYS_MPC85xx_PCIE1_OFFSET
-CONFIG_SYS_MPC85xx_PCIE2_OFFSET
-CONFIG_SYS_MPC85xx_PCIE3_OFFSET
-CONFIG_SYS_MPC85xx_PCIE4_OFFSET
-CONFIG_SYS_MPC85xx_PCIX2_ADDR
-CONFIG_SYS_MPC85xx_PCIX2_OFFSET
-CONFIG_SYS_MPC85xx_PCIX_ADDR
-CONFIG_SYS_MPC85xx_PCIX_OFFSET
-CONFIG_SYS_MPC85xx_PIC_OFFSET
-CONFIG_SYS_MPC85xx_QE_OFFSET
-CONFIG_SYS_MPC85xx_SATA
-CONFIG_SYS_MPC85xx_SATA1_ADDR
-CONFIG_SYS_MPC85xx_SATA1_OFFSET
-CONFIG_SYS_MPC85xx_SATA2_ADDR
-CONFIG_SYS_MPC85xx_SATA2_OFFSET
-CONFIG_SYS_MPC85xx_SCFG
-CONFIG_SYS_MPC85xx_SCFG_OFFSET
-CONFIG_SYS_MPC85xx_SERDES1_ADDR
-CONFIG_SYS_MPC85xx_SERDES1_OFFSET
-CONFIG_SYS_MPC85xx_SERDES2_ADDR
-CONFIG_SYS_MPC85xx_SERDES2_OFFSET
-CONFIG_SYS_MPC85xx_TDM_OFFSET
-CONFIG_SYS_MPC85xx_USB
-CONFIG_SYS_MPC85xx_USB1_ADDR
-CONFIG_SYS_MPC85xx_USB1_OFFSET
-CONFIG_SYS_MPC85xx_USB1_PHY_ADDR
-CONFIG_SYS_MPC85xx_USB1_PHY_OFFSET
-CONFIG_SYS_MPC85xx_USB2_ADDR
-CONFIG_SYS_MPC85xx_USB2_OFFSET
-CONFIG_SYS_MPC85xx_USB2_PHY_ADDR
-CONFIG_SYS_MPC85xx_USB2_PHY_OFFSET
-CONFIG_SYS_MPC8xxx_DDR2_OFFSET
-CONFIG_SYS_MPC8xxx_DDR3_OFFSET
-CONFIG_SYS_MPC8xxx_DDR_OFFSET
-CONFIG_SYS_MPC8xxx_PIC_ADDR
CONFIG_SYS_MRAM_BASE
-CONFIG_SYS_MRAM_SIZE
-CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
CONFIG_SYS_NAND_AMASK
CONFIG_SYS_NAND_BASE
CONFIG_SYS_NAND_BASE2
CONFIG_SYS_NAND_U_BOOT_RELOC_SP
CONFIG_SYS_NAND_U_BOOT_SIZE
CONFIG_SYS_NAND_U_BOOT_START
-CONFIG_SYS_NONCACHED_MEMORY
CONFIG_SYS_NOR0_CSPR
CONFIG_SYS_NOR0_CSPR_EARLY
CONFIG_SYS_NOR0_CSPR_EXT
CONFIG_SYS_OMAP_ABE_SYSCK
CONFIG_SYS_ONENAND_BASE
CONFIG_SYS_ONENAND_BLOCK_SIZE
-CONFIG_SYS_OR_TIMING_MRAM
CONFIG_SYS_OSCIN_FREQ
CONFIG_SYS_OSPR_OFFSET
CONFIG_SYS_PACNT
CONFIG_SYS_SDRAM_BASE0
CONFIG_SYS_SDRAM_BASE1
CONFIG_SYS_SDRAM_BASE2
-CONFIG_SYS_SDRAM_CFG
CONFIG_SYS_SDRAM_CFG1
CONFIG_SYS_SDRAM_CFG2
CONFIG_SYS_SDRAM_CTRL
CONFIG_SYS_SDRC_TR_VAL
CONFIG_SYS_SDRC_TR_VAL1
CONFIG_SYS_SDRC_TR_VAL2
-CONFIG_SYS_SD_VOLTAGE
CONFIG_SYS_SEC_MON_ADDR
CONFIG_SYS_SEC_MON_OFFSET
CONFIG_SYS_SERIAL0
CONFIG_SYS_UBOOT_BASE
CONFIG_SYS_UBOOT_START
CONFIG_SYS_UEC
-CONFIG_SYS_UEC2_ETH_TYPE
-CONFIG_SYS_UEC2_INTERFACE_SPEED
-CONFIG_SYS_UEC2_INTERFACE_TYPE
CONFIG_SYS_UEC2_PHY_ADDR
-CONFIG_SYS_UEC2_RX_CLK
-CONFIG_SYS_UEC2_TX_CLK
-CONFIG_SYS_UEC2_UCC_NUM
CONFIG_SYS_USB_OHCI_REGS_BASE
CONFIG_SYS_VCXK_ACKNOWLEDGE_DDR
CONFIG_SYS_VCXK_ACKNOWLEDGE_PIN
CONFIG_SYS_VCXK_REQUEST_DDR
CONFIG_SYS_VCXK_REQUEST_PIN
CONFIG_SYS_VCXK_REQUEST_PORT
-CONFIG_SYS_VIDEO_LOGO_MAX_SIZE
CONFIG_SYS_VSC7385_BASE
CONFIG_SYS_VSC7385_BASE_PHYS
CONFIG_SYS_VSC7385_BR_PRELIM
CONFIG_TWL6030_POWER
CONFIG_UBIFS_VOLUME
CONFIG_UBI_PART
-CONFIG_UBI_SIZE
CONFIG_UBOOTPATH
CONFIG_UBOOT_SECTOR_COUNT
CONFIG_UBOOT_SECTOR_START
CONFIG_USBD_PRODUCTID_GSERIAL
CONFIG_USBD_PRODUCT_NAME
CONFIG_USBD_VENDORID
-CONFIG_USBNET_DEV_ADDR
CONFIG_USB_BOOTING
CONFIG_USB_DEVICE
CONFIG_USB_EXT2_BOOT
projects / platform / kernel / u-boot.git / blobdiff