* Authors:
* Jérôme Glisse <jglisse@redhat.com>
*/
+#ifdef HAVE_CONFIG_H
+#include <config.h>
+#endif
#include <stdbool.h>
#include <assert.h>
#include <errno.h>
#include <sys/mman.h>
#include <sys/ioctl.h>
#include "drm.h"
+#include "libdrm.h"
#include "xf86drm.h"
#include "radeon_drm.h"
#include "radeon_surface.h"
CHIP_KAVERI,
CHIP_KABINI,
CHIP_HAWAII,
+ CHIP_MULLINS,
CHIP_LAST,
};
surf_minify(surf, surf->level+i, surf->bpe, i, xalign, yalign, zalign, offset);
/* level0 and first mipmap need to have alignment */
offset = surf->bo_size;
- if ((i == 0)) {
+ if (i == 0) {
offset = ALIGN(offset, surf->bo_alignment);
}
}
surf_minify(surf, surf->level+i, surf->bpe, i, xalign, yalign, zalign, offset);
/* level0 and first mipmap need to have alignment */
offset = surf->bo_size;
- if ((i == 0)) {
+ if (i == 0) {
offset = ALIGN(offset, surf->bo_alignment);
}
}
surf_minify(surf, surf->level+i, surf->bpe, i, xalign, yalign, zalign, offset);
/* level0 and first mipmap need to have alignment */
offset = surf->bo_size;
- if ((i == 0)) {
+ if (i == 0) {
offset = ALIGN(offset, surf->bo_alignment);
}
}
}
/* level0 and first mipmap need to have alignment */
offset = surf->bo_size;
- if ((i == 0)) {
+ if (i == 0) {
offset = ALIGN(offset, surf->bo_alignment);
}
}
surf_minify(surf, level+i, bpe, i, xalign, yalign, zalign, offset);
/* level0 and first mipmap need to have alignment */
offset = surf->bo_size;
- if ((i == 0)) {
+ if (i == 0) {
offset = ALIGN(offset, surf->bo_alignment);
}
}
tileb = tilew * tileh * bpe * surf->nsamples;
/* slices per tile */
slice_pt = 1;
- if (tileb > tile_split) {
+ if (tileb > tile_split && tile_split) {
slice_pt = tileb / tile_split;
}
tileb = tileb / slice_pt;
}
/* level0 and first mipmap need to have alignment */
offset = surf->bo_size;
- if ((i == 0)) {
+ if (i == 0) {
offset = ALIGN(offset, surf->bo_alignment);
}
}
/* default value */
surf->mtilea = 1;
surf->bankw = 1;
- surf->bankw = 1;
+ surf->bankh = 1;
surf->tile_split = 64;
surf->stencil_tile_split = 64;
}
si_surf_minify(surf, surf->level+i, surf->bpe, i, xalign, yalign, zalign, slice_align, offset);
/* level0 and first mipmap need to have alignment */
offset = surf->bo_size;
- if ((i == 0)) {
+ if (i == 0) {
offset = ALIGN(offset, surf->bo_alignment);
}
if (surf->flags & RADEON_SURF_HAS_TILE_MODE_INDEX) {
si_surf_minify(surf, level+i, bpe, i, xalign, yalign, zalign, slice_align, offset);
/* level0 and first mipmap need to have alignment */
offset = surf->bo_size;
- if ((i == 0)) {
+ if (i == 0) {
offset = ALIGN(offset, alignment);
}
if (surf->flags & RADEON_SURF_HAS_TILE_MODE_INDEX) {
tileb = tilew * tileh * bpe * surf->nsamples;
/* slices per tile */
slice_pt = 1;
- if (tileb > tile_split) {
+ if (tileb > tile_split && tile_split) {
slice_pt = tileb / tile_split;
}
tileb = tileb / slice_pt;
return si_surface_init_1d(surf_man, surf, level, bpe, tile_mode, offset, i);
}
/* level0 and first mipmap need to have alignment */
- aligned_offset = surf->bo_size;
- if ((i == 0)) {
+ aligned_offset = offset = surf->bo_size;
+ if (i == 0) {
aligned_offset = ALIGN(aligned_offset, surf->bo_alignment);
}
if (surf->flags & RADEON_SURF_HAS_TILE_MODE_INDEX) {
#define CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_16x16 12
#define CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_16x32 13
#define CIK__PIPE_CONFIG__ADDR_SURF_P8_32x64_32x32 14
+#define CIK__PIPE_CONFIG__ADDR_SURF_P16_32X32_8X16 16
+#define CIK__PIPE_CONFIG__ADDR_SURF_P16_32X32_16X16 17
#define CIK__GB_TILE_MODE__TILE_SPLIT(x) (((x) >> 11) & 0x7)
#define CIK__TILE_SPLIT__64B 0
#define CIK__TILE_SPLIT__128B 1
case CIK__PIPE_CONFIG__ADDR_SURF_P8_32x64_32x32:
*num_pipes = 8;
break;
+ case CIK__PIPE_CONFIG__ADDR_SURF_P16_32X32_8X16:
+ case CIK__PIPE_CONFIG__ADDR_SURF_P16_32X32_16X16:
+ *num_pipes = 16;
+ break;
}
}
switch (CIK__GB_TILE_MODE__TILE_SPLIT(gb_tile_mode)) {
sample_split = 1;
break;
case CIK__SAMPLE_SPLIT__2:
- sample_split = 1;
+ sample_split = 2;
break;
case CIK__SAMPLE_SPLIT__4:
sample_split = 4;
/* default value */
surf->mtilea = 1;
surf->bankw = 1;
- surf->bankw = 1;
+ surf->bankh = 1;
surf->tile_split = 64;
surf->stencil_tile_split = 64;
}
/* slices per tile */
slice_pt = 1;
- if (tileb > tile_split) {
+ if (tileb > tile_split && tile_split) {
slice_pt = tileb / tile_split;
tileb = tileb / slice_pt;
}
/* ===========================================================================
* public API
*/
-struct radeon_surface_manager *radeon_surface_manager_new(int fd)
+drm_public struct radeon_surface_manager *
+radeon_surface_manager_new(int fd)
{
struct radeon_surface_manager *surf_man;
return NULL;
}
-void radeon_surface_manager_free(struct radeon_surface_manager *surf_man)
+drm_public void
+radeon_surface_manager_free(struct radeon_surface_manager *surf_man)
{
free(surf_man);
}
return 0;
}
-int radeon_surface_init(struct radeon_surface_manager *surf_man,
- struct radeon_surface *surf)
+drm_public int
+radeon_surface_init(struct radeon_surface_manager *surf_man,
+ struct radeon_surface *surf)
{
unsigned mode, type;
int r;
return surf_man->surface_init(surf_man, surf);
}
-int radeon_surface_best(struct radeon_surface_manager *surf_man,
- struct radeon_surface *surf)
+drm_public int
+radeon_surface_best(struct radeon_surface_manager *surf_man,
+ struct radeon_surface *surf)
{
unsigned mode, type;
int r;