Fix merge problems

[platform/kernel/u-boot.git] / post / cpu / ppc4xx / spr.c

diff --git a/post/cpu/ppc4xx/spr.c b/post/cpu/ppc4xx/spr.c
index c12e378..110df6e 100644 (file)
--- a/post/cpu/ppc4xx/spr.c
+++ b/post/cpu/ppc4xx/spr.c
@@ -35,14 +35,18 @@
  * corresponding table value.
  */
 
-#ifdef CONFIG_POST
-
 #include <post.h>
 
 #if CONFIG_POST & CFG_POST_SPR
 
 #include <asm/processor.h>
 
+#ifdef CONFIG_4xx_DCACHE
+#include <asm/mmu.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+#endif
+
 static struct {
        int number;
        char * name;
@@ -72,7 +76,9 @@ static struct {
        {0x3b,  "CSRR1",        0x00000000,     0x00000000},
        {0x3d,  "DEAR",         0x00000000,     0x00000000},
        {0x3e,  "ESR",          0x00000000,     0x00000000},
+#ifdef CONFIG_440
        {0x3f,  "IVPR",         0xffff0000,     0x00000000},
+#endif
        {0x100, "USPRG0",       0x00000000,     0x00000000},
        {0x104, "SPRG4",        0x00000000,     0x00000000},
        {0x105, "SPRG5",        0x00000000,     0x00000000},
@@ -164,6 +170,10 @@ int spr_post_test (int flags)
        };
        unsigned long (*get_spr) (void) = (void *) code;
 
+#ifdef CONFIG_4xx_DCACHE
+       /* disable cache */
+       change_tlb(gd->bd->bi_memstart, gd->bd->bi_memsize, TLB_WORD2_I_ENABLE);
+#endif
        for (i = 0; i < spr_test_list_size; i++) {
                int num = spr_test_list[i].number;
 
@@ -180,9 +190,12 @@ int spr_post_test (int flags)
                        ret = -1;
                }
        }
+#ifdef CONFIG_4xx_DCACHE
+       /* enable cache */
+       change_tlb(gd->bd->bi_memstart, gd->bd->bi_memsize, 0);
+#endif
 
        return ret;
 }
 
 #endif /* CONFIG_POST & CFG_POST_SPR */
-#endif /* CONFIG_POST */