*
* Author: Pavel Kolesnikov <concord@emcraft.com>
*
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier: GPL-2.0+
*/
/* define DEBUG for debugging output (obviously ;-)) */
#include <common.h>
#include <watchdog.h>
-#if defined(CONFIG_POST) && (defined(CONFIG_440EPX) || defined(CONFIG_440GRX))
+#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
#include <post.h>
-#if CONFIG_POST & CFG_POST_ECC
+#if CONFIG_POST & CONFIG_SYS_POST_ECC
/*
* MEMORY ECC test
#include <asm/processor.h>
#include <asm/mmu.h>
#include <asm/io.h>
-#include <ppc440.h>
+#include <asm/ppc440.h>
DECLARE_GLOBAL_DATA_PTR;
+#if defined(DEBUG)
const static uint8_t syndrome_codes[] = {
0xF4, 0XF1, 0XEC, 0XEA, 0XE9, 0XE6, 0XE5, 0XE3,
0XDC, 0XDA, 0XD9, 0XD6, 0XD5, 0XD3, 0XCE, 0XCB,
0X1C, 0X1A, 0X19, 0X16, 0X15, 0X13, 0X0E, 0X0B,
0x80, 0x40, 0x20, 0x10, 0x08, 0x04, 0x02, 0x01
};
+#endif
#define ECC_START_ADDR 0x10
#define ECC_STOP_ADDR 0x2000
clear_and_enable_ecc();
out_be32(ecc_mem, ECC_PATTERN);
out_be32(ecc_mem + 1, ECC_PATTERN);
+ ppcDcbf((u32)ecc_mem);
/* Verify no ECC error reading back */
value = in_be32(ecc_mem);
/* Test for correctable error by creating a one-bit error */
out_be32(ecc_mem, ECC_PATTERN_CORR);
+ ppcDcbf((u32)ecc_mem);
clear_and_enable_ecc();
value = in_be32(ecc_mem);
disable_ecc();
/* Test for uncorrectable error by creating a two-bit error */
out_be32(ecc_mem, ECC_PATTERN_UNCORR);
+ ppcDcbf((u32)ecc_mem);
clear_and_enable_ecc();
value = in_be32(ecc_mem);
disable_ecc();
/* Remove error from SDRAM and enable ECC. */
out_be32(ecc_mem, ECC_PATTERN);
+ ppcDcbf((u32)ecc_mem);
clear_and_enable_ecc();
return ret;
debug("ecc_post_test() returning %d\n", ret);
return ret;
}
-#endif /* CONFIG_POST & CFG_POST_ECC */
-#endif /* defined(CONFIG_POST) && ... */
+#endif /* CONFIG_POST & CONFIG_SYS_POST_ECC */
+#endif /* defined(CONFIG_440EPX) || defined(CONFIG_440GRX) */