/* RISC-V opcode list
- Copyright (C) 2011-2018 Free Software Foundation, Inc.
+ Copyright (C) 2011-2019 Free Software Foundation, Inc.
Contributed by Andrew Waterman (andrew@sifive.com).
Based on MIPS target.
const struct riscv_opcode riscv_opcodes[] =
{
/* name, xlen, isa, operands, match, mask, match_func, pinfo. */
-{"unimp", 0, {"C", 0}, "", 0, 0xffffU, match_opcode, 0 },
+{"unimp", 0, {"C", 0}, "", 0, 0xffffU, match_opcode, INSN_ALIAS },
{"unimp", 0, {"I", 0}, "", MATCH_CSRRW | (CSR_CYCLE << OP_SH_CSR), 0xffffffffU, match_opcode, 0 }, /* csrw cycle, x0 */
{"ebreak", 0, {"C", 0}, "", MATCH_C_EBREAK, MASK_C_EBREAK, match_opcode, INSN_ALIAS },
{"ebreak", 0, {"I", 0}, "", MATCH_EBREAK, MASK_EBREAK, match_opcode, 0 },
{"and", 0, {"I", 0}, "d,s,j", MATCH_ANDI, MASK_ANDI, match_opcode, INSN_ALIAS },
{"beqz", 0, {"C", 0}, "Cs,Cp", MATCH_C_BEQZ, MASK_C_BEQZ, match_opcode, INSN_ALIAS|INSN_CONDBRANCH },
{"beqz", 0, {"I", 0}, "s,p", MATCH_BEQ, MASK_BEQ | MASK_RS2, match_opcode, INSN_ALIAS|INSN_CONDBRANCH },
+{"beq", 0, {"C", 0}, "Cs,Cz,Cp", MATCH_C_BEQZ, MASK_C_BEQZ, match_opcode, INSN_ALIAS|INSN_CONDBRANCH },
{"beq", 0, {"I", 0}, "s,t,p", MATCH_BEQ, MASK_BEQ, match_opcode, INSN_CONDBRANCH },
{"blez", 0, {"I", 0}, "t,p", MATCH_BGE, MASK_BGE | MASK_RS1, match_opcode, INSN_ALIAS|INSN_CONDBRANCH },
{"bgez", 0, {"I", 0}, "s,p", MATCH_BGE, MASK_BGE | MASK_RS2, match_opcode, INSN_ALIAS|INSN_CONDBRANCH },
-{"ble", 0, {"I", 0}, "t,s,p", MATCH_BGE, MASK_BGE, match_opcode, INSN_ALIAS|INSN_CONDBRANCH },
-{"bleu", 0, {"I", 0}, "t,s,p", MATCH_BGEU, MASK_BGEU, match_opcode, INSN_ALIAS|INSN_CONDBRANCH },
{"bge", 0, {"I", 0}, "s,t,p", MATCH_BGE, MASK_BGE, match_opcode, INSN_CONDBRANCH },
{"bgeu", 0, {"I", 0}, "s,t,p", MATCH_BGEU, MASK_BGEU, match_opcode, INSN_CONDBRANCH },
+{"ble", 0, {"I", 0}, "t,s,p", MATCH_BGE, MASK_BGE, match_opcode, INSN_ALIAS|INSN_CONDBRANCH },
+{"bleu", 0, {"I", 0}, "t,s,p", MATCH_BGEU, MASK_BGEU, match_opcode, INSN_ALIAS|INSN_CONDBRANCH },
{"bltz", 0, {"I", 0}, "s,p", MATCH_BLT, MASK_BLT | MASK_RS2, match_opcode, INSN_ALIAS|INSN_CONDBRANCH },
{"bgtz", 0, {"I", 0}, "t,p", MATCH_BLT, MASK_BLT | MASK_RS1, match_opcode, INSN_ALIAS|INSN_CONDBRANCH },
{"blt", 0, {"I", 0}, "s,t,p", MATCH_BLT, MASK_BLT, match_opcode, INSN_CONDBRANCH },
{"bgtu", 0, {"I", 0}, "t,s,p", MATCH_BLTU, MASK_BLTU, match_opcode, INSN_ALIAS|INSN_CONDBRANCH },
{"bnez", 0, {"C", 0}, "Cs,Cp", MATCH_C_BNEZ, MASK_C_BNEZ, match_opcode, INSN_ALIAS|INSN_CONDBRANCH },
{"bnez", 0, {"I", 0}, "s,p", MATCH_BNE, MASK_BNE | MASK_RS2, match_opcode, INSN_ALIAS|INSN_CONDBRANCH },
+{"bne", 0, {"C", 0}, "Cs,Cz,Cp", MATCH_C_BNEZ, MASK_C_BNEZ, match_opcode, INSN_ALIAS|INSN_CONDBRANCH },
{"bne", 0, {"I", 0}, "s,t,p", MATCH_BNE, MASK_BNE, match_opcode, INSN_CONDBRANCH },
{"addi", 0, {"C", 0}, "Ct,Cc,CK", MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN, match_c_addi4spn, INSN_ALIAS },
{"addi", 0, {"C", 0}, "d,CU,Cj", MATCH_C_ADDI, MASK_C_ADDI, match_rd_nonzero, INSN_ALIAS },
{"add", 0, {"I", 0}, "d,s,t", MATCH_ADD, MASK_ADD, match_opcode, 0 },
/* This is used for TLS, where the fourth arg is %tprel_add, to get a reloc
applied to an add instruction, for relaxation to use. */
-{"add", 0, {"I", 0}, "d,s,t,0",MATCH_ADD, MASK_ADD, match_opcode, 0 },
+{"add", 0, {"I", 0}, "d,s,t,1",MATCH_ADD, MASK_ADD, match_opcode, 0 },
{"add", 0, {"I", 0}, "d,s,j", MATCH_ADDI, MASK_ADDI, match_opcode, INSN_ALIAS },
{"la", 0, {"I", 0}, "d,B", 0, (int) M_LA, match_never, INSN_MACRO },
{"lla", 0, {"I", 0}, "d,B", 0, (int) M_LLA, match_never, INSN_MACRO },
{"fence", 0, {"I", 0}, "", MATCH_FENCE | MASK_PRED | MASK_SUCC, MASK_FENCE | MASK_RD | MASK_RS1 | MASK_IMM, match_opcode, INSN_ALIAS },
{"fence", 0, {"I", 0}, "P,Q", MATCH_FENCE, MASK_FENCE | MASK_RD | MASK_RS1 | (MASK_IMM & ~MASK_PRED & ~MASK_SUCC), match_opcode, 0 },
{"fence.i", 0, {"I", 0}, "", MATCH_FENCE_I, MASK_FENCE | MASK_RD | MASK_RS1 | MASK_IMM, match_opcode, 0 },
+{"fence.tso", 0, {"I", 0}, "", MATCH_FENCE_TSO, MASK_FENCE_TSO | MASK_RD | MASK_RS1, match_opcode, INSN_ALIAS },
{"rdcycle", 0, {"I", 0}, "d", MATCH_RDCYCLE, MASK_RDCYCLE, match_opcode, INSN_ALIAS },
{"rdinstret", 0, {"I", 0}, "d", MATCH_RDINSTRET, MASK_RDINSTRET, match_opcode, INSN_ALIAS },
{"rdtime", 0, {"I", 0}, "d", MATCH_RDTIME, MASK_RDTIME, match_opcode, INSN_ALIAS },
{"remuw", 64, {"M", 0}, "d,s,t", MATCH_REMUW, MASK_REMUW, match_opcode, 0 },
/* Single-precision floating-point instruction subset */
-{"frsr", 0, {"F", 0}, "d", MATCH_FRCSR, MASK_FRCSR, match_opcode, 0 },
-{"fssr", 0, {"F", 0}, "s", MATCH_FSCSR, MASK_FSCSR | MASK_RD, match_opcode, 0 },
-{"fssr", 0, {"F", 0}, "d,s", MATCH_FSCSR, MASK_FSCSR, match_opcode, 0 },
-{"frcsr", 0, {"F", 0}, "d", MATCH_FRCSR, MASK_FRCSR, match_opcode, 0 },
-{"fscsr", 0, {"F", 0}, "s", MATCH_FSCSR, MASK_FSCSR | MASK_RD, match_opcode, 0 },
-{"fscsr", 0, {"F", 0}, "d,s", MATCH_FSCSR, MASK_FSCSR, match_opcode, 0 },
-{"frrm", 0, {"F", 0}, "d", MATCH_FRRM, MASK_FRRM, match_opcode, 0 },
-{"fsrm", 0, {"F", 0}, "s", MATCH_FSRM, MASK_FSRM | MASK_RD, match_opcode, 0 },
-{"fsrm", 0, {"F", 0}, "d,s", MATCH_FSRM, MASK_FSRM, match_opcode, 0 },
-{"fsrmi", 0, {"F", 0}, "d,Z", MATCH_FSRMI, MASK_FSRMI, match_opcode, 0 },
-{"fsrmi", 0, {"F", 0}, "Z", MATCH_FSRMI, MASK_FSRMI | MASK_RD, match_opcode, 0 },
-{"frflags", 0, {"F", 0}, "d", MATCH_FRFLAGS, MASK_FRFLAGS, match_opcode, 0 },
-{"fsflags", 0, {"F", 0}, "s", MATCH_FSFLAGS, MASK_FSFLAGS | MASK_RD, match_opcode, 0 },
-{"fsflags", 0, {"F", 0}, "d,s", MATCH_FSFLAGS, MASK_FSFLAGS, match_opcode, 0 },
-{"fsflagsi", 0, {"F", 0}, "d,Z", MATCH_FSFLAGSI, MASK_FSFLAGSI, match_opcode, 0 },
-{"fsflagsi", 0, {"F", 0}, "Z", MATCH_FSFLAGSI, MASK_FSFLAGSI | MASK_RD, match_opcode, 0 },
+{"frcsr", 0, {"F", 0}, "d", MATCH_FRCSR, MASK_FRCSR, match_opcode, INSN_ALIAS },
+{"frsr", 0, {"F", 0}, "d", MATCH_FRCSR, MASK_FRCSR, match_opcode, INSN_ALIAS },
+{"fscsr", 0, {"F", 0}, "s", MATCH_FSCSR, MASK_FSCSR | MASK_RD, match_opcode, INSN_ALIAS },
+{"fscsr", 0, {"F", 0}, "d,s", MATCH_FSCSR, MASK_FSCSR, match_opcode, INSN_ALIAS },
+{"fssr", 0, {"F", 0}, "s", MATCH_FSCSR, MASK_FSCSR | MASK_RD, match_opcode, INSN_ALIAS },
+{"fssr", 0, {"F", 0}, "d,s", MATCH_FSCSR, MASK_FSCSR, match_opcode, INSN_ALIAS },
+{"frrm", 0, {"F", 0}, "d", MATCH_FRRM, MASK_FRRM, match_opcode, INSN_ALIAS },
+{"fsrm", 0, {"F", 0}, "s", MATCH_FSRM, MASK_FSRM | MASK_RD, match_opcode, INSN_ALIAS },
+{"fsrm", 0, {"F", 0}, "d,s", MATCH_FSRM, MASK_FSRM, match_opcode, INSN_ALIAS },
+{"fsrmi", 0, {"F", 0}, "d,Z", MATCH_FSRMI, MASK_FSRMI, match_opcode, INSN_ALIAS },
+{"fsrmi", 0, {"F", 0}, "Z", MATCH_FSRMI, MASK_FSRMI | MASK_RD, match_opcode, INSN_ALIAS },
+{"frflags", 0, {"F", 0}, "d", MATCH_FRFLAGS, MASK_FRFLAGS, match_opcode, INSN_ALIAS },
+{"fsflags", 0, {"F", 0}, "s", MATCH_FSFLAGS, MASK_FSFLAGS | MASK_RD, match_opcode, INSN_ALIAS },
+{"fsflags", 0, {"F", 0}, "d,s", MATCH_FSFLAGS, MASK_FSFLAGS, match_opcode, INSN_ALIAS },
+{"fsflagsi", 0, {"F", 0}, "d,Z", MATCH_FSFLAGSI, MASK_FSFLAGSI, match_opcode, INSN_ALIAS },
+{"fsflagsi", 0, {"F", 0}, "Z", MATCH_FSFLAGSI, MASK_FSFLAGSI | MASK_RD, match_opcode, INSN_ALIAS },
{"flw", 32, {"F", "C", 0}, "D,Cm(Cc)", MATCH_C_FLWSP, MASK_C_FLWSP, match_opcode, INSN_ALIAS|INSN_DREF|INSN_4_BYTE },
{"flw", 32, {"F", "C", 0}, "CD,Ck(Cs)", MATCH_C_FLW, MASK_C_FLW, match_opcode, INSN_ALIAS|INSN_DREF|INSN_4_BYTE },
{"flw", 0, {"F", 0}, "D,o(s)", MATCH_FLW, MASK_FLW, match_opcode, INSN_DREF|INSN_4_BYTE },
{"fcvt.q.lu", 64, {"Q", 0}, "D,s,m", MATCH_FCVT_Q_LU, MASK_FCVT_Q_LU, match_opcode, 0 },
/* Compressed instructions. */
+{"c.unimp", 0, {"C", 0}, "", 0, 0xffffU, match_opcode, 0 },
{"c.ebreak", 0, {"C", 0}, "", MATCH_C_EBREAK, MASK_C_EBREAK, match_opcode, 0 },
{"c.jr", 0, {"C", 0}, "d", MATCH_C_JR, MASK_C_JR, match_rd_nonzero, INSN_BRANCH },
{"c.jalr", 0, {"C", 0}, "d", MATCH_C_JALR, MASK_C_JALR, match_rd_nonzero, INSN_JSR },
{"r", 0, {"I", 0}, "O4,F3,F2,d,S,T,R", 0, 0, match_opcode, 0 },
{"r", 0, {"I", 0}, "O4,F3,F2,D,S,T,R", 0, 0, match_opcode, 0 },
+{"r4", 0, {"I", 0}, "O4,F3,F2,d,s,t,r", 0, 0, match_opcode, 0 },
+{"r4", 0, {"I", 0}, "O4,F3,F2,D,s,t,r", 0, 0, match_opcode, 0 },
+{"r4", 0, {"I", 0}, "O4,F3,F2,d,S,t,r", 0, 0, match_opcode, 0 },
+{"r4", 0, {"I", 0}, "O4,F3,F2,D,S,t,r", 0, 0, match_opcode, 0 },
+{"r4", 0, {"I", 0}, "O4,F3,F2,d,s,T,r", 0, 0, match_opcode, 0 },
+{"r4", 0, {"I", 0}, "O4,F3,F2,D,s,T,r", 0, 0, match_opcode, 0 },
+{"r4", 0, {"I", 0}, "O4,F3,F2,d,S,T,r", 0, 0, match_opcode, 0 },
+{"r4", 0, {"I", 0}, "O4,F3,F2,D,S,T,r", 0, 0, match_opcode, 0 },
+{"r4", 0, {"I", 0}, "O4,F3,F2,d,s,t,R", 0, 0, match_opcode, 0 },
+{"r4", 0, {"I", 0}, "O4,F3,F2,D,s,t,R", 0, 0, match_opcode, 0 },
+{"r4", 0, {"I", 0}, "O4,F3,F2,d,S,t,R", 0, 0, match_opcode, 0 },
+{"r4", 0, {"I", 0}, "O4,F3,F2,D,S,t,R", 0, 0, match_opcode, 0 },
+{"r4", 0, {"I", 0}, "O4,F3,F2,d,s,T,R", 0, 0, match_opcode, 0 },
+{"r4", 0, {"I", 0}, "O4,F3,F2,D,s,T,R", 0, 0, match_opcode, 0 },
+{"r4", 0, {"I", 0}, "O4,F3,F2,d,S,T,R", 0, 0, match_opcode, 0 },
+{"r4", 0, {"I", 0}, "O4,F3,F2,D,S,T,R", 0, 0, match_opcode, 0 },
+
{"i", 0, {"I", 0}, "O4,F3,d,s,j", 0, 0, match_opcode, 0 },
{"i", 0, {"I", 0}, "O4,F3,D,s,j", 0, 0, match_opcode, 0 },
{"i", 0, {"I", 0}, "O4,F3,d,S,j", 0, 0, match_opcode, 0 },
{"i", 0, {"I", 0}, "O4,F3,d,o(s)", 0, 0, match_opcode, 0 },
{"i", 0, {"I", 0}, "O4,F3,D,o(s)", 0, 0, match_opcode, 0 },
-{"s", 0, {"I", 0}, "O4,F3,d,o(s)", 0, 0, match_opcode, 0 },
-{"s", 0, {"I", 0}, "O4,F3,D,o(s)", 0, 0, match_opcode, 0 },
+{"s", 0, {"I", 0}, "O4,F3,t,q(s)", 0, 0, match_opcode, 0 },
+{"s", 0, {"I", 0}, "O4,F3,T,q(s)", 0, 0, match_opcode, 0 },
{"sb", 0, {"I", 0}, "O4,F3,s,t,p", 0, 0, match_opcode, 0 },
{"sb", 0, {"I", 0}, "O4,F3,S,t,p", 0, 0, match_opcode, 0 },
{"sb", 0, {"I", 0}, "O4,F3,s,T,p", 0, 0, match_opcode, 0 },
{"sb", 0, {"I", 0}, "O4,F3,S,T,p", 0, 0, match_opcode, 0 },
-{"sb", 0, {"I", 0}, "O4,F3,t,q(s)", 0, 0, match_opcode, 0 },
-{"sb", 0, {"I", 0}, "O4,F3,T,q(s)", 0, 0, match_opcode, 0 },
+{"b", 0, {"I", 0}, "O4,F3,s,t,p", 0, 0, match_opcode, 0 },
+{"b", 0, {"I", 0}, "O4,F3,S,t,p", 0, 0, match_opcode, 0 },
+{"b", 0, {"I", 0}, "O4,F3,s,T,p", 0, 0, match_opcode, 0 },
+{"b", 0, {"I", 0}, "O4,F3,S,T,p", 0, 0, match_opcode, 0 },
{"u", 0, {"I", 0}, "O4,d,u", 0, 0, match_opcode, 0 },
{"u", 0, {"I", 0}, "O4,D,u", 0, 0, match_opcode, 0 },
{"uj", 0, {"I", 0}, "O4,d,a", 0, 0, match_opcode, 0 },
{"uj", 0, {"I", 0}, "O4,D,a", 0, 0, match_opcode, 0 },
+{"j", 0, {"I", 0}, "O4,d,a", 0, 0, match_opcode, 0 },
+{"j", 0, {"I", 0}, "O4,D,a", 0, 0, match_opcode, 0 },
+
{"cr", 0, {"C", 0}, "O2,CF4,d,CV", 0, 0, match_opcode, 0 },
{"cr", 0, {"C", 0}, "O2,CF4,D,CV", 0, 0, match_opcode, 0 },
{"cr", 0, {"C", 0}, "O2,CF4,d,CT", 0, 0, match_opcode, 0 },
{"ci", 0, {"C", 0}, "O2,CF3,d,Co", 0, 0, match_opcode, 0 },
{"ci", 0, {"C", 0}, "O2,CF3,D,Co", 0, 0, match_opcode, 0 },
-{"ciw", 0, {"C", 0}, "O2,CF3,Ct,C8", 0, 0, match_opcode, 0 },
-{"ciw", 0, {"C", 0}, "O2,CF3,CD,C8", 0, 0, match_opcode, 0 },
+{"ciw", 0, {"C", 0}, "O2,CF3,Ct,C8", 0, 0, match_opcode, 0 },
+{"ciw", 0, {"C", 0}, "O2,CF3,CD,C8", 0, 0, match_opcode, 0 },
+
+{"ca", 0, {"C", 0}, "O2,CF6,CF2,Cs,Ct", 0, 0, match_opcode, 0 },
+{"ca", 0, {"C", 0}, "O2,CF6,CF2,CS,Ct", 0, 0, match_opcode, 0 },
+{"ca", 0, {"C", 0}, "O2,CF6,CF2,Cs,CD", 0, 0, match_opcode, 0 },
+{"ca", 0, {"C", 0}, "O2,CF6,CF2,CS,CD", 0, 0, match_opcode, 0 },
{"cb", 0, {"C", 0}, "O2,CF3,Cs,Cp", 0, 0, match_opcode, 0 },
{"cb", 0, {"C", 0}, "O2,CF3,CS,Cp", 0, 0, match_opcode, 0 },