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Version 2.25
[platform/upstream/binutils.git] / opcodes / micromips-opc.c
diff --git a/opcodes/micromips-opc.c b/opcodes/micromips-opc.c
index 4b1cdd7..71b2dfe 100644 (file)
--- a/opcodes/micromips-opc.c
+++ b/opcodes/micromips-opc.c
@@ -107,6 +107,7 @@ decode_micromips_operand (const char *p)
        case 'F': MSB (5, 11, 33, TRUE, 64);     /* (33 .. 64), 64-bit op */
        case 'G': MSB (5, 11, 33, FALSE, 64);    /* (33 .. 64), 64-bit op */
        case 'H': MSB (5, 11, 1, FALSE, 64);     /* (1 .. 32), 64-bit op */
+       case 'J': HINT (10, 16);
        case 'T': INT_ADJ (10, 16, 511, 0, FALSE);      /* (-512 .. 511) << 0 */
        case 'U': INT_ADJ (10, 16, 511, 1, FALSE);      /* (-512 .. 511) << 1 */
        case 'V': INT_ADJ (10, 16, 511, 2, FALSE);      /* (-512 .. 511) << 2 */
@@ -158,7 +159,6 @@ decode_micromips_operand (const char *p)
     case '7': REG (2, 14, ACC);
     case '8': HINT (6, 14);
 
-    case 'B': HINT (10, 16);
     case 'C': HINT (23, 3);
     case 'D': REG (5, 11, FP);
     case 'E': REG (5, 21, COPRO);
@@ -202,8 +202,8 @@ decode_micromips_operand (const char *p)
 #define TRAP   INSN_NO_DELAY_SLOT
 #define LM     INSN_LOAD_MEMORY
 #define SM     INSN_STORE_MEMORY
-#define COD    INSN_COPROC_MOVE_DELAY
-#define LCD    INSN_LOAD_COPROC_DELAY
+#define CM     INSN_COPROC_MOVE
+#define LC     INSN_LOAD_COPROC
 #define BD16   INSN2_BRANCH_DELAY_16BIT        /* Used in pinfo2.  */
 #define BD32   INSN2_BRANCH_DELAY_32BIT        /* Used in pinfo2.  */
 
@@ -296,10 +296,6 @@ const struct mips_opcode micromips_opcodes[] =
 {"li",                 "md,mI",            0xec00,     0xfc00, WR_1,                   0,              I1,             0,      0 },
 {"li",                 "t,j",          0x30000000, 0xfc1f0000, WR_1,                   INSN2_ALIAS,    I1,             0,      0 }, /* addiu */
 {"li",                 "t,i",          0x50000000, 0xfc1f0000, WR_1,                   INSN2_ALIAS,    I1,             0,      0 }, /* ori */
-#if 0
-/* Disabled until we can handle 48-bit opcodes.  */
-{"li",                 "s,I",  0x7c0000010000, 0xfc00001f0000, WR_t,                   0,              I3,             0,      0 }, /* li48 */
-#endif
 {"li",                 "t,I",          0,    (int) M_LI,       INSN_MACRO,             0,              I1,             0,      0 },
 {"move",               "d,s",          0,    (int) M_MOVE,     INSN_MACRO,             0,              I1,             0,      0 },
 {"move",               "mp,mj",            0x0c00,     0xfc00, WR_1|RD_2,              0,              I1,             0,      0 },
@@ -625,10 +621,10 @@ const struct mips_opcode micromips_opcodes[] =
 {"dmtc0",              "t,G,H",        0x580002fc, 0xfc00c7ff, RD_1|WR_C0|WR_CC,       0,              I3,             0,      0 },
 {"dmtgc0",             "t,G",          0x580006fc, 0xfc00ffff, RD_1|WR_C0|WR_CC,       0,              0,              IVIRT64, 0 },
 {"dmtgc0",             "t,G,H",        0x580006fc, 0xfc00c7ff, RD_1|WR_C0|WR_CC,       0,              0,              IVIRT64, 0 },
-{"dmfc1",              "t,S",          0x5400243b, 0xfc00ffff, WR_1|RD_2|FP_S|LCD,     0,              I3,             0,      0 },
-{"dmfc1",              "t,G",          0x5400243b, 0xfc00ffff, WR_1|RD_2|FP_S|LCD,     0,              I3,             0,      0 },
-{"dmtc1",              "t,G",          0x54002c3b, 0xfc00ffff, RD_1|WR_2|FP_S|COD,     0,              I3,             0,      0 },
-{"dmtc1",              "t,S",          0x54002c3b, 0xfc00ffff, RD_1|WR_2|FP_S|COD,     0,              I3,             0,      0 },
+{"dmfc1",              "t,S",          0x5400243b, 0xfc00ffff, WR_1|RD_2|FP_S|LC,      0,              I3,             0,      0 },
+{"dmfc1",              "t,G",          0x5400243b, 0xfc00ffff, WR_1|RD_2|FP_S|LC,      0,              I3,             0,      0 },
+{"dmtc1",              "t,G",          0x54002c3b, 0xfc00ffff, RD_1|WR_2|FP_S|CM,      0,              I3,             0,      0 },
+{"dmtc1",              "t,S",          0x54002c3b, 0xfc00ffff, RD_1|WR_2|FP_S|CM,      0,              I3,             0,      0 },
 {"dmfc2",              "t,G",          0x00006d3c, 0xfc00ffff, WR_1|RD_C2,             0,              I3,             0,      0 },
 /*{"dmfc2",            "t,G,H",        0x58000283, 0xfc001fff, WR_1|RD_C2,             0,              I3,             0,      0 },*/
 {"dmtc2",              "t,G",          0x00007d3c, 0xfc00ffff, RD_1|WR_C2|WR_CC,       0,              I3,             0,      0 },
@@ -692,7 +688,7 @@ const struct mips_opcode micromips_opcodes[] =
 {"floor.w.d",          "T,V",          0x54004b3b, 0xfc00ffff, WR_1|RD_2|FP_S|FP_D,    0,              I1,             0,      0 },
 {"floor.w.s",          "T,V",          0x54000b3b, 0xfc00ffff, WR_1|RD_2|FP_S,         0,              I1,             0,      0 },
 {"hypcall",            "",             0x0000c37c, 0xffffffff, TRAP,                   0,              0,              IVIRT,  0 },
-{"hypcall",            "B",            0x0000c37c, 0xfc00ffff, TRAP,                   0,              0,              IVIRT,  0 },
+{"hypcall",            "+J",           0x0000c37c, 0xfc00ffff, TRAP,                   0,              0,              IVIRT,  0 },
 {"ins",                        "t,r,+A,+B",    0x0000000c, 0xfc00003f, WR_1|RD_2,              0,              I1,             0,      0 },
 {"iret",               "",             0x0000d37c, 0xffffffff, NODS,                   0,              0,              MC,     0 },
 {"jr",                 "mj",               0x4580,     0xffe0, RD_1|UBD,               0,              I1,             0,      0 },
@@ -825,13 +821,13 @@ const struct mips_opcode micromips_opcodes[] =
 {"maddu",              "7,s,t",        0x00001abc, 0xfc003fff, RD_2|RD_3|MOD_a,        0,              0,              D32,    0 },
 {"mfc0",               "t,G",          0x000000fc, 0xfc00ffff, WR_1|RD_C0,             0,              I1,             0,      0 },
 {"mfc0",               "t,G,H",        0x000000fc, 0xfc00c7ff, WR_1|RD_C0,             0,              I1,             0,      0 },
-{"mfc1",               "t,S",          0x5400203b, 0xfc00ffff, WR_1|RD_2|FP_S|LCD,     0,              I1,             0,      0 },
-{"mfc1",               "t,G",          0x5400203b, 0xfc00ffff, WR_1|RD_2|FP_S|LCD,     0,              I1,             0,      0 },
+{"mfc1",               "t,S",          0x5400203b, 0xfc00ffff, WR_1|RD_2|FP_S|LC,      0,              I1,             0,      0 },
+{"mfc1",               "t,G",          0x5400203b, 0xfc00ffff, WR_1|RD_2|FP_S|LC,      0,              I1,             0,      0 },
 {"mfc2",               "t,G",          0x00004d3c, 0xfc00ffff, WR_1|RD_C2,             0,              I1,             0,      0 },
 {"mfgc0",              "t,G",          0x000004fc, 0xfc00ffff, WR_1|RD_C0,             0,              0,              IVIRT,  0 },
 {"mfgc0",              "t,G,H",        0x000004fc, 0xfc00c7ff, WR_1|RD_C0,             0,              0,              IVIRT,  0 },
-{"mfhc1",              "t,S",          0x5400303b, 0xfc00ffff, WR_1|RD_2|FP_D|LCD,     0,              I1,             0,      0 },
-{"mfhc1",              "t,G",          0x5400303b, 0xfc00ffff, WR_1|RD_2|FP_D|LCD,     0,              I1,             0,      0 },
+{"mfhc1",              "t,S",          0x5400303b, 0xfc00ffff, WR_1|RD_2|FP_D|LC,      0,              I1,             0,      0 },
+{"mfhc1",              "t,G",          0x5400303b, 0xfc00ffff, WR_1|RD_2|FP_D|LC,      0,              I1,             0,      0 },
 {"mfhc2",              "t,G",          0x00008d3c, 0xfc00ffff, WR_1|RD_C2,             0,              I1,             0,      0 },
 {"mfhi",               "mj",               0x4600,     0xffe0, WR_1|RD_HI,             0,              I1,             0,      0 },
 {"mfhi",               "s",            0x00000d7c, 0xffe0ffff, WR_1|RD_HI,             0,              I1,             0,      0 },
@@ -871,13 +867,13 @@ const struct mips_opcode micromips_opcodes[] =
 {"msubu",              "7,s,t",        0x00003abc, 0xfc003fff, RD_2|RD_3|MOD_a,        0,              0,              D32,    0 },
 {"mtc0",               "t,G",          0x000002fc, 0xfc00ffff, RD_1|WR_C0|WR_CC,       0,              I1,             0,      0 },
 {"mtc0",               "t,G,H",        0x000002fc, 0xfc00c7ff, RD_1|WR_C0|WR_CC,       0,              I1,             0,      0 },
-{"mtc1",               "t,S",          0x5400283b, 0xfc00ffff, RD_1|WR_2|FP_S|COD,     0,              I1,             0,      0 },
-{"mtc1",               "t,G",          0x5400283b, 0xfc00ffff, RD_1|WR_2|FP_S|COD,     0,              I1,             0,      0 },
+{"mtc1",               "t,S",          0x5400283b, 0xfc00ffff, RD_1|WR_2|FP_S|CM,      0,              I1,             0,      0 },
+{"mtc1",               "t,G",          0x5400283b, 0xfc00ffff, RD_1|WR_2|FP_S|CM,      0,              I1,             0,      0 },
 {"mtc2",               "t,G",          0x00005d3c, 0xfc00ffff, RD_1|WR_C2|WR_CC,       0,              I1,             0,      0 },
 {"mtgc0",              "t,G",          0x000006fc, 0xfc00ffff, RD_1|WR_C0|WR_CC,       0,              0,              IVIRT,  0 },
 {"mtgc0",              "t,G,H",        0x000006fc, 0xfc00c7ff, RD_1|WR_C0|WR_CC,       0,              0,              IVIRT,  0 },
-{"mthc1",              "t,S",          0x5400383b, 0xfc00ffff, RD_1|WR_2|FP_D|COD,     0,              I1,             0,      0 },
-{"mthc1",              "t,G",          0x5400383b, 0xfc00ffff, RD_1|WR_2|FP_D|COD,     0,              I1,             0,      0 },
+{"mthc1",              "t,S",          0x5400383b, 0xfc00ffff, RD_1|WR_2|FP_D|CM,      0,              I1,             0,      0 },
+{"mthc1",              "t,G",          0x5400383b, 0xfc00ffff, RD_1|WR_2|FP_D|CM,      0,              I1,             0,      0 },
 {"mthc2",              "t,G",          0x00009d3c, 0xfc00ffff, RD_1|WR_C2|WR_CC,       0,              I1,             0,      0 },
 {"mthi",               "s",            0x00002d7c, 0xffe0ffff, RD_1|WR_HI,             0,              I1,             0,      0 },
 {"mthi",               "s,7",          0x0000207c, 0xffe03fff, RD_1|WR_HI,             0,              0,              D32,    0 },
@@ -967,7 +963,7 @@ const struct mips_opcode micromips_opcodes[] =
 {"sdbbp",              "",                 0x46c0,     0xffff, TRAP,                   0,              I1,             0,      0 },
 {"sdbbp",              "",             0x0000db7c, 0xffffffff, TRAP,                   0,              I1,             0,      0 },
 {"sdbbp",              "mO",               0x46c0,     0xfff0, TRAP,                   0,              I1,             0,      0 },
-{"sdbbp",              "B",            0x0000db7c, 0xfc00ffff, TRAP,                   0,              I1,             0,      0 },
+{"sdbbp",              "+J",           0x0000db7c, 0xfc00ffff, TRAP,                   0,              I1,             0,      0 },
 {"sdc1",               "T,o(b)",       0xb8000000, 0xfc000000, RD_1|RD_3|SM|FP_D,      0,              I1,             0,      0 },
 {"sdc1",               "E,o(b)",       0xb8000000, 0xfc000000, RD_1|RD_3|SM|FP_D,      0,              I1,             0,      0 },
 {"sdc1",               "T,A(b)",       0,    (int) M_SDC1_AB,  INSN_MACRO,             INSN2_M_FP_D,   I1,             0,      0 },
@@ -1070,7 +1066,7 @@ const struct mips_opcode micromips_opcodes[] =
 {"sync",               "1",            0x00006b7c, 0xffe0ffff, NODS,                   0,              I1,             0,      0 },
 {"synci",              "o(b)",         0x42000000, 0xffe00000, RD_2|SM,                0,              I1,             0,      0 },
 {"syscall",            "",             0x00008b7c, 0xffffffff, TRAP,                   0,              I1,             0,      0 },
-{"syscall",            "B",            0x00008b7c, 0xfc00ffff, TRAP,                   0,              I1,             0,      0 },
+{"syscall",            "+J",           0x00008b7c, 0xfc00ffff, TRAP,                   0,              I1,             0,      0 },
 {"teqi",               "s,j",          0x41c00000, 0xffe00000, RD_1|TRAP,              0,              I1,             0,      0 },
 {"teq",                        "s,t",          0x0000003c, 0xfc00ffff, RD_1|RD_2|TRAP,         0,              I1,             0,      0 },
 {"teq",                        "s,t,|",        0x0000003c, 0xfc000fff, RD_1|RD_2|TRAP,         0,              I1,             0,      0 },
@@ -1125,7 +1121,7 @@ const struct mips_opcode micromips_opcodes[] =
 {"ush",                        "t,A(b)",       0,    (int) M_USH_AB,   INSN_MACRO,             0,              I1,             0,      0 },
 {"usw",                        "t,A(b)",       0,    (int) M_USW_AB,   INSN_MACRO,             0,              I1,             0,      0 },
 {"wait",               "",             0x0000937c, 0xffffffff, NODS,                   0,              I1,             0,      0 },
-{"wait",               "B",            0x0000937c, 0xfc00ffff, NODS,                   0,              I1,             0,      0 },
+{"wait",               "+J",           0x0000937c, 0xfc00ffff, NODS,                   0,              I1,             0,      0 },
 {"wrpgpr",             "t,r",          0x0000f17c, 0xfc00ffff, RD_2,                   0,              I1,             0,      0 },
 {"wsbh",               "t,r",          0x00007b3c, 0xfc00ffff, WR_1|RD_2,              0,              I1,             0,      0 },
 {"xor",                        "mf,mt,mg",         0x4440,     0xffc0, MOD_1|RD_3,             0,              I1,             0,      0 },
Domain: System / Toolchain;